Taiwan Semiconductor Manufacturing Company Research Articles

Electronically and Independently Controllable Quadrature Sinusoidal Oscillator with Low Output Impedances

This work presents the quadrature sinusoidal oscillator using two Voltage Differencing-Differential Input Buffered Amplifiers (VD-DIBAs), two resistors, and two capacitors. The VD-DIBA is an electronically controllable active building block with high input and low output impedances that can connect to other circuits directly without the buffers. With these distinguished features, the VD-DIBA is employed in this design. The proposed oscillator can produce two sine waves with a phase shift of 90 degrees. Over the entire tuning frequency range, the magnitude of the quadrature output voltages is constant. The proposed oscillator is independently adjustable in terms of frequency and oscillation condition. Moreover, the frequency of oscillation can be electronically and linearly adjusted by the bias currents. The condition of oscillation is adjustable by resistors, R_1 and R_2. The performances of the proposed quadrature oscillator are tested through the PSpice simulation and the experiment. In the simulation, the VD-DIBA is built from the 0.18um Taiwan Semiconductor Manufacturing Company (TSMC) CMOS process with +-0.9V supply voltages. In the experiment, the VD-DIBA is implemented using the commercial ICs, LM13700, and AD830 with +-5V supply voltages. The simulated Total Harmonic Distortion (THD) values of the output voltages, V_o1 and V_o2 at f_0 = 1.03MHz are 1.63% and 1.81%, respectively. The experimental THD values of the output voltages, V_o1 and V_o2 at f_0 = 536.6kHz, are 1.43% and 1.00%, respectively.

The Fleeting Possibility of Merging the World’s Largest Chip Manufacturer in 2017: The Pain of Chinese Chip Industry

This article examines a possible Chinese semiconductor industry’s merger and acquisition in 2017, the year before the Sino-US trade war and US high-tech sanctions against China. The feasibility of a merger between Tsinghua Unigroup and Taiwan Semiconductor Manufacturing Company is thoroughly examined as well as their development history and the current financial standing. The financial data collected form the two companies’ annual report was analyzed using multiple corporate valuating models. We discovered that the industrial policy and financial reports in 2017 favored the merger, but the combination ultimately collapsed, which was quite a pity for Chinese chip sector. The research contributes to an in-depth comprehension of China’s semiconductor business and serves as a model for future financial analyses of comparable sectors.

THETA: A High-Efficiency Training Accelerator for DNNs With Triple-Side Sparsity Exploration

Training deep neural networks (DNNs) on edge devices has attracted increasing attention in real-world applications for domain adaption and privacy protection. However, deploying DNN training on resource-limited edge devices is challenging as there are massive computations and data transportation in training. To address this issue, we propose an energy-efficient training accelerator in this work by employing a hybrid compression strategy. Here, various data redundancies are fully exploited, and the real triple-side sparsity is achieved. Hence, the computational complexity is drastically reduced with negligible accuracy loss across a range of transfer learning tasks. To facilitate triple-side zero-skipping operations during different training stages, we first present a novel sparse data representation and a triple-sparsity index matching scheme. Second, a sparse tensor processing unit (STPU) arranged in a hierarchical structure is developed, which enables a flexible dataflow to process convolutional (Conv) and fully connected (FC) layers with diverse computational patterns throughout the entire training. Third, an auxiliary processing unit (APU) is designed to execute some postprocessing operations, such as rectified linear unit (ReLU) and on-the-fly pruning. Finally, the training accelerator is implemented under Taiwan Semiconductor Manufacturing Company (TSMC) 28-nm process and evaluated on multiple benchmarks. The experimental results show that THETA achieves 7.28–22.32 tera operations per second (TOPS) and 45.24–133.70 TOPS/W in performance and energy efficiency, reducing 40– <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$72\times $ </tex-math></inline-formula> training time and 19– <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$63\times $ </tex-math></inline-formula> energy consumption over dense training, respectively. Compared with the prior art, our design offers <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.6\times $ </tex-math></inline-formula> throughput and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.9\times $ </tex-math></inline-formula> energy efficiency, respectively.

Foundry Service of CMOS MEMS Processes and the Case Study of the Flow Sensor

The complementary metal-oxide-semiconductor (CMOS) process is the main stream to fabricate integrated circuits (ICs) in the semiconductor industry. Microelectromechanical systems (MEMS), when combined with CMOS electronics to form the CMOS MEMS process, have the merits of small features, low power consumption, on-chip circuitry, and high sensitivity to develop microsensors and micro actuators. Firstly, the authors review the educational CMOS MEMS foundry service provided by the Taiwan Semiconductor Research Institute (TSRI) allied with the United Microelectronics Corporation (UMC) and the Taiwan Semiconductor Manufacturing Company (TSMC). Taiwan’s foundry service of ICs is leading in the world. Secondly, the authors show the new flow sensor integrated with an instrumentation amplifier (IA) fabricated by the latest UMC 0.18 µm CMOS MEMS process as the case study. The new flow sensor adopted the self-heating resistive-thermal-detector (RTD) to sense the flow speed. This self-heating RTD half-bridge alone gives a normalized output sensitivity of 138 µV/V/(m/s)/mW only. After being integrated with an on-chip amplifier gain of 20 dB, the overall sensitivity of the flow sensor was measured and substantially improved to 1388 µV/V/(m/s)/mW for the flow speed range of 0–5 m/s. Finally, the advantages of the CMOS MEMS flow sensors are justified and discussed by the testing results.

Design and Analysis of High-Gain and Compact Single-Input Differential-Output Low Noise Amplifier for 5G Applications

This letter describes the design, analysis, and testing of a 28-GHz single-input differential-output (SIDO) low-noise amplifier (LNA) with a noise figure of 2.5 dB, compact size (0.25 mm²), and high gain (22.3 dB). The proposed LNA was fabricated using the Taiwan Semiconductor Manufacturing Company (TSMC) 65-nm CMOS process. This amplifier contains a two-stage common-source (CS) buffer amplifier for a low-noise design and combines CS and common-gate transistors for converting single-ended signal into differential signal. A novel method of common-mode rejection ratio optimization is used to determine the optimal phase compensation transmission line and transistor size to reduce gain and phase imbalances simultaneously. The gain and phase imbalances were 0.042 dB and 2.6° at 28 GHz, respectively. Compared with published LNAs, this SIDO LNA achieved the high figure of merits (FoMs) of 7.17 and 2.27, respectively. Therefore, this LNA can be used for 5G NR band of n257 (26.5-29.5 GHz), n258 (24.25-27.5 GHz), and n261 (27.5-28.35 GHz).

A 0.6-dB Low Loss and 3–165 GHz Wideband Phase Difference Sub-THz Coupler in 0.18-μm CMOS

In this letter, a new 90° coupler with a symmetric coupled-line structure featuring the use of the tuning multiple floating metals technique is designed, analyzed, and verified for subterahertz (THz) applications; this new coupler was fabricated on the standard Taiwan Semiconductor Manufacturing Company (TSMC) 0.18-μm 1P6M CMOS process. With the proposed structure, the impedances of even and odd modes can be designed individually to simultaneously optimize the performance in terms of insertion loss, phase balance, amplitude balance, isolation, and reflection coefficients. The bandwidths of phase imbalance (± 3°) and amplitude imbalance (± 1 dB) are 162 and 100 GHz, respectively. Reflection coefficients less than -20 dB are reached at 0.2-184 GHz, and isolation higher than 20 dB is from 0.2 to 200 GHz.

Decision-based virtual metrology for advanced process control to empower smart production and an empirical study for semiconductor manufacturing

Virtual metrology (VM) has been employed to improve the performance of advanced process control for semiconductor manufacturing. A number of VM models have been proposed to predict the quality characteristics for the wafers that have not been sampled and measured. However, little research has been done to address the interrelations between the VM model and associated decisions for advanced process control and yield enhancement. There is a research need for developing a framework that can integrate the confidence level of VM prediction and domain knowledge to derive appropriate decisions for real-time control. To fill the gaps, this study aims to develop a decision-based virtual metrology framework that integrates clustering and regression models to enhance the prediction and ensure the decision quality for the R2R controller. In particular, Isolation Forest is employed to cluster the data group for multi-recipes and multi-tools. Random Forest Regression is developed for the prediction model for each category respectively to enhance the accuracy of predicted results. Furthermore, this approach designs an overall confidence score based on data integrity and predicted results to suggest the optimal decision rules for R2R control in real time. This approach is validated with an empirical study in a leading semiconductor manufacturing company in Taiwan. Indeed, the results have demonstrated practical viability and the developed solution has been implemented.

1.2 V Differential Difference Transconductance Amplifier and Its Application in Mixed-Mode Universal Filter.

This paper presents a new mixed-mode universal filter based on a differential difference transconductance amplifier (DDTA). Unlike the conventional transconductance amplifier (TA), this DDTA has both advantages of the TA and the differential difference amplifier (DDA). The proposed filter can offer four-mode operations of second-order transfer functions into a single topology, namely, voltage-mode (VM), current-mode (CM), transadmittance-mode (TAM), and transimpedance-mode (TIM) transfer functions. Each operation mode offers five standard filtering responses; therefore, at least twenty filtering transfer functions can be obtained. For the filtering transfer functions, the matching conditions for the input and passive component are absent. The natural frequency and the quality factor can be set orthogonally and electronically controlled. The performance of the proposed topology was evaluated by PSPICE simulator using the 0.18 µm CMOS technology from the Taiwan Semiconductor Manufacturing Company (TSMC). The voltage supply was 1.2 V and the power dissipation of the DDTA was 66 µW. The workability of the filter was confirmed through experimental test by DDTA-based LM13600 discrete-component integrated circuits.

Redefining Monitoring Rules for Intelligent Fault Detection and Classification via CNN Transfer Learning for Smart Manufacturing

Fault detection and classification has been employed to enhance yield and product quality for smart semiconductor manufacturing. For early detection of abnormal events that cause defects, the status variables identification data collected by the sensors embedded in advanced machines can be analyzed to derive the actions for advanced process control and advanced equipment control. However, the validity and effectiveness of fault detection and classification technologies may highly depend on domain knowledge and experience of the process engineers who should redefine the monitoring rules quickly when new process excursion occurred especially when ramping up new technologies and products. Motivated by realistic needs, this study aims to propose a novel strategy to empower intelligent fault detection and classification that employed convolutional neural network to analyze the feature SVID data and determine the conditions of the wafers, while shorten the cycle time for self-learning from domain knowledge and redefining new monitoring rules for fault classification in real time. This approach is validated with an empirical study in a leading semiconductor manufacturing company in Taiwan. The results have demonstrated the practical viability of the developed solution.

A 0.4-V High-Gain Low-Noise Amplifier Using a Variable-Frequency Image-Rejection Technology

A 0.4-V high-gain low-noise amplifier (LNA) using a variable-frequency image-rejection technology in Taiwan Semiconductor Manufacturing Company (TSMC) 0.18-<inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS process has been proposed. By using forward body biasing and folded topology, the supply voltage and power consumption can be reduced. For achieving low power consumption and small chip area, a feedback capacitor is used to shrink the size of the inductors of the input impedance matching. Moreover, a gain-enhancement-and-image-rejection (GEIR) circuit including an inductor and a variable capacitor is proposed for achieving GEIR simultaneously. The image-rejection frequency can be altered for avoiding strong image signals by the variable capacitor. The proposed LNA shows the measured results including a 15-dB power gain, a 2.6-dB noise figure, and a &#x2212;13-dBm input third-order intercept point at 2.4 GHz, respectively. And the measured variable image rejection ratio ranges from 14 to 39 dBc around 3&#x2013;3.6 GHz for avoiding strong image signals. The measured <inline-formula> <tex-math notation="LaTeX">$P_{\text {dc}} $ </tex-math></inline-formula> is 0.8 mW.

Hardware architecture of a digital piecewise linear chaotic map with perturbation for pseudorandom number generation

Piecewise linear chaotic map (PWLCM) is a simple chaotic system popularly used for generating pseudorandom numbers (PRN). Digital implementation of PWLCM degrades the randomness of the pseudorandom number due to the finite precision effect. The current paper presents a digital 1-dimensional PWLCM that mitigates the degradation of digital chaos by cascading the chaotic map with a three-stage XORed shift register that perturbs the output of the PWLCM. We further perturb the output of the shift register using a one-stage XOR post-processing. We also present the hardware architecture of the proposed system to generate a high throughput PRN sequence. The designed architecture is synthesized on Xilinx Zynq 7000 Field Programmable Gate Array (FPGA) and Application Specific Integrated Circuit (ASIC) using TSMC (Taiwan Semiconductor Manufacturing Company) 90 nm CMOS technology. We experimentally validate the randomness of the output sequence using NIST test suite 800–22. In addition, we also perform security analyses such as phase space, key sensitivity, correlation, and information entropy. The statistical and security analysis confirms the efficiency of the proposed design in terms of randomness. The synthesis result demonstrates the achieved throughput as 1.296 Gbps at 81 MHz operating frequency on Zynq 7000 FPGA, whereas a throughput of 1.696 Gbps at 106 MHz operating frequency is achieved on ASIC.

A new high speed charge and high efficiency Li-Ion battery charger interface using pulse control technique

A new Li-Ion battery charger interface (BCI) using pulse control (PC) technique is designed and analyzed in this paper. Thanks to the use of PC technique, the main standards of the Li-Ion battery charger, i.e. fast charge, small surface area and high efficiency, are achieved. The proposed charger achieves full charge in forty-one minutes passing by the constant current (CC) charging mode which also included the start-up and the constant voltage mode (CV) charging mode. It designed, simulated and layouted which occupies a small size area 0.1 mm2 by using Taiwan Semiconductor Manufacturing Company 180 nm complementary metal oxide semi-conductor technology (TSMC 180 nm CMOS) technology in Cadence Virtuoso software. The battery voltage VBAT varies between 2.9 V to 4.35 V and the maximum battery current IBAT is 2.1 A in CC charging mode, according to a maximum input voltage VIN equal 5 V. The maximum charging efficiency reaches 98%.

Third order inverse multifunction filter employing MOS resistors and capacitors

AbstractThis paper presents a systematic approach for the realization of multifunction filter that includes third order inverse low pass filter (ILPF), band pass filter (IBPF), and high pass filter (IHPF) using two Operational Transresistance Amplifiers (OTRAs), MOS resistors, and few number of capacitors. An operational activity of inverse filter configuration (IFC) can be easily realized by proper selection of switches. In ideal case, third order of the filter characterizes a total roll‐off of 60 dB/decade but the proposed design offers a roll‐off in the range of 48.09 dB/decade to 57.74 dB/decade which may arises due to passive component tolerance and some design parameters. The proposed design brings an improvement in roll‐off around 20%–44% in comparison to existing literatures. The multifunction filter frequency response (ILPF, IBPF, and IHPF) is observed by using PSPICE simulation in which the core of the filter “OTRA” is integrated with 180 nm Taiwan Semiconductor Manufacturing Company (TSMC) CMOS technology parameter. In addition to simulation results, hardware implementation of the proposed filter configuration validates the theoretical aspect of filter design.

A 40-nm 118.44-TOPS/W Voltage-Sensing Compute-in-Memory RRAM Macro With Write Verification and Multi-Bit Encoding

Computing-in-memory (CIM) architectures have paved the way for energy-efficient artificial intelligence (AI) systems while outperforming von Neumann architectures. In particular, resistive RAM (RRAM)-based CIM has drawn attention due to high cell density, non-volatility, and compatibility with a CMOS process. RRAM also exhibits the feasibility of high-capacity CIM with multi-bit encoding per cell exploiting an appropriate ON/OFF resistance ratio. However, the prior work regarding multi-level RRAM cells mainly focused on achieving higher bit resolution in write without consideration of CIM performance. Thus, the circuit solution to achieve multi-bit encoding per cell dedicated to RRAM-based CIM (RCIM) is of importance to support high-capacity AI systems with reliable CIM performance. This article presents a 256 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> 256 CIM multi-level RRAM macro featuring iterative write with verification to achieve reliable multi-bit encoding per cell and the voltage-sensing readout circuit to surmount the underlying logic ambiguity in RCIM architectures. In addition, we also demonstrate the key design space of a fabricated RRAM array in the write operation with extensive experiments. The test chip fabricated in a Taiwan Semiconductor Manufacturing Company (TSMC) 40-nm CMOS and RRAM process achieves a peak energy efficiency of 118.44 TOPS/W in the ternary-weight multiply-and-accumulate (MAC) operation and demonstrates the feasibility of multi-level RCIM with voltage-sensing RCIM.

A Dual-Mode W-Band Eight-Way Parallel–Series Power-Combining PA With +18-dBm P sat and 15.1% PAE in 65-nm CMOS Technology

This letter presents the design of a Dual-mode W-band eight-way power-combining power amplifier (PA) implemented in Taiwan Semiconductor Manufacturing Company (TSMC) 65-nm CMOS technology ( $f_{t}$ / $f_{{max}}$ : 210 GHz/240 GHz). A configurable parallel-series-based eight-way power combine technique is proposed to achieve high output power with high power efficiency near half of $f_{t}$ . The eight-way power-combiner is consisted of two transformer-based parallel two-way differential combiners and a coupled-line-based series combiner to achieve high passive efficiency and compact layout. The proposed PA achieves a measured peak gain of 30.9 dB with a bandwidth (BW) of 7.5 GHz. The PA has $P_{{sat}}$ of +18 dBm with an 1dB output compression point (OP1dB) of +13.8 dBm and a peak PAE of 15.1% in high-power mode. In the low-power mode (LPM), the measured $P_{{sat}}$ , OP1dB, and peak PAE are +13.6, +9.1 dBm, and 10.3%, respectively. The PAE is enhanced by 3.4% points at a 6-dB back-off in LPM. The core area of the proposed PA is 0.3 mm².

An Evolutionary Normalization Algorithm for Signed Floating-Point Multiply-Accumulate Operation

In the era of digital signal processing, like graphics and computation systems, multiplication-accumulation is one of the prime operations. A MAC unit is a vital component of a digital system, like different Fast Fourier Transform (FFT) algorithms, convolution, image processing algorithms, etcetera. In the domain of digital signal processing, the use of normalization architecture is very vast. The main objective of using normalization is to perform comparison and shift operations. In this research paper, an evolutionary approach for designing an optimized normalization algorithm is proposed using basic logical blocks such as Multiplexer, Adder etc. The proposed normalization algorithm is further used in designing an 8 × 8 bit Signed Floating-Point Multiply-Accumulate (SFMAC) architecture. Since the SFMAC can accept an 8-bit significand and a 3-bit exponent, the input to the said architecture can be somewhere between −(7.96872)10 to + (7.96872)10. The proposed architecture is designed and implemented using the Cadence Virtuoso using 90 and 130 nm technologies (in Generic Process Design Kit (GPDK) and Taiwan Semiconductor Manufacturing Company (TSMC), respectively). To reduce the power consumption of the proposed normalization architecture, techniques such as “block enabling” and “clock gating” are used rigorously. According to the analysis done on Cadence, the proposed architecture uses the least amount of power compared to its current predecessors.

Chua's Oscillator With OTA Based Memcapacitor Emulator

A charge-controlled memcapacitor emulator design based on the current-mode technique has been proposed in this research work. The physical realization of a memcapacitor is an open problem that motivates creating newer designs for memcapacitor emulator circuits. The memcapacitor emulator comprises an operational transconductance amplifier (OTA), an active component and has additional passive elements. Memcapacitor, abstracted to have a (pinched) hysteresis loop, is emulated in this work, can be also observed as a nonlinear capacitor with memory in its physical form. The simulations are carried out using 0.18 μm (Taiwan Semiconductor Manufacturing Company) TSMC technology and a ±1.2 V supply voltage to analyse robustness of design through process corner, temperature variation, and non-volatility. Experimental validations are performed using ICs CA3080 on breadboard. An application of chaotic oscillator and adaptive learning circuit using a memcapacitor emulator circuit is shown as a practical case study.

Electronically Tunable Flux-Controlled Resistorless Memristor Emulator

This article demonstrates a voltage differencing inverting buffered amplifier (VDIBA)-based resistorless flux-controlled memristor emulator circuit with tunability. Two VDIBA blocks serve as active components, and a grounded capacitor serving as a passive part. The proposed emulator design is devoid of multipliers and resistors through effective utilization of port relationships. Including tunability, the suggested emulator functions in both incremental and decremental modes. It accurately depicts the attributes of an ideal memristor up to 12.7 MHz and consumes a total power of 1.34 mW. The mathematical analysis is substantiated through Cadence simulation in 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu$</tex-math> </inline-formula> m Taiwan Semiconductor Manufacturing Company (TSMC) technology with the supply voltage of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\pm$</tex-math> </inline-formula> 1 V. Nonideal, single/parallel, Monte-Carlo sampling and corner analysis were conducted to confirm circuit resilience. The nonvolatile nature of the presented emulator model has also been included. A breadboard prototype incorporating the ICs CA3080 and LT1193 are built to conduct an experimental demonstration. The experimental findings were consistent with the theoretical expectations and simulation results.

An EGFET Based Common Source Amplifier as a Low-Frequency Instrumentation Amplifier for Sensitivity Measurement on RuO2 Lactic Acid Biosensor

In this study, a low-frequency instrumentation amplifier (LFIA) integrated with an extended-gate field-effect transistor (EGFET) is presented to realize the simplicity common source amplifier (CSA) structure. The proposed EGFET CSA was developed by the 0.18-&#x03BC;m CMOS process technology of Taiwan Semiconductor Manufacturing Company (TSMC). The EGFET CSA has low frequency and noise immunity function, and it can effectively output the response signal, with good stability and effectively improve the sensitivity, not susceptible to environmental factors, easy to replace, and low cost. Moreover, the simple circuit design of the EGFET CSA was used to analyze the sensing characteristics and to improve the stability of the ruthenium dioxide (RuO₂) lactic acid (LA) biosensor. Therefore, the EGFET CSA is suitable for LA detection. The simple process of the EGFET CSA was used to analyze the sensing characteristics and to improve the stability of the ruthenium dioxide (RuO₂) lactic acid (LA) biosensor. An arrayed potentiometric LA biosensor based on the RuO₂ thin film was proposed and manufactured in this study. The experimental results indicated that the EGFET CSA as a low-frequency instrumentation amplifier has achieved a good sensitivity (53.41mV/mM) and satisfactory linearity (0.997) on the RuO₂ LA biosensor as compared with the V-T measurement system.

A 2.3–5-GHz LC-VCO With Source Damping Resistors to Suppress 1/f Noise Up-Conversion

Two RF CMOS voltage-controlled oscillators (VCOs) with source damping resistors to suppress 1/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${f}$ </tex-math></inline-formula> noise up-conversion are presented in this letter. Two important parameters: the phase deviation from the first harmonic term of the ideal impulse sensitivity function (ISF), and the initial phase of the first harmonic term of channel current, dominate the 1/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${f}$ </tex-math></inline-formula> noise up-conversion. Based on the outcome, the effects of the source damping resistors on the two phases are analyzed and two VCO prototypes are designed. Implemented in Taiwan Semiconductor Manufacturing Company 180 nm RF CMOS process, the VCOs achieve 64.7% and 50% frequency tuning range at 2.3–4.5 and 3–5 GHz, respectively, and perform phase noise (PN) of −131.03, −129.28, and −124.98 dBc/Hz at 1 MHz offset from output frequencies of 2.33, 3.057, and 4.57 GHz separately.