Taiwan Semiconductor Manufacturing Company Research Articles

All‐digital power‐efficient integrating frequency difference‐to‐digital converter for GHz frequency‐locking

This study presents an all-digital power-efficient integrating frequency difference-to-digital converter (iFDDC) and explores its applications in gigahertz (GHz) frequency-locking. The iFDDC utilises a bi-directional gated delay line (BDGDL) to detect and accumulate the frequency difference between two GHz signals and digitises the result with ultra-low power consumption. The built-in integration of the iFDDC ensures that the in-band quantisation noise of the BDGDL and digital controlled oscillator (DCO) is first-order suppressed. The all-digital realisation of the iFDDC makes it fully compatible with technology scaling. The effectiveness of the proposed iFDDC is verified using the simulation results of a 5 GHz frequency-locked loop designed in a Taiwan Semiconductor Manufacturing Company (TSMC) 65 nm 1.2 V complementary metal-oxide-semiconductor (CMOS). The iFDDC consumes only 474 µW, offering the lowest power/frequency efficiency among reported FDDCs. The DCO locks to 5 GHz reference in <10 cycles.

A dual‐band high‐gain EBG resonator antenna fed by dipole in CMOS process

AbstractA high‐gain dual‐band electromagnetic band‐gap (EBG) resonator antenna (ERA) which is suitable for 60 GHz short‐range communication and 77 GHz vehicle collision avoidance application is proposed. The EBG is constructed by two identical slabs over a fully reflective ground plane. A dipole in Taiwan Semiconductor Manufacturing Company (TSMC) 65 nm process is employed to serve as a feeder of the resonator. By combining the frequency resonances of the EBG and the feeding chip fabricated on the LTCC substrate, the proposed ERA obtains dual‐band performance. Furthermore, the proposed ERA achieves a high gain by designing two slabs to have phase shifts introduced by multiple reflections of the wave between the ground and slabs at double certain frequency points. Finally, the prototype of the antenna is simulated by High Frequency Structure Simulator (HFSS) and good agreement was achieved between simulated and measured data. The results demonstrate that it has a 10‐dB return loss bandwidth of 57.7 to 62.1 GHz and 75.2 to 77.4 GHz. Radiation efficiencies are 27.5% and 60% with 8.3 dBi gain and 14.4 dBi gain at 60 and 77 GHz, respectively.

A Novel Low-Power Synchronous Preamble Data Line Chip Design for Oscillator Control Interface

In this paper, a novel low-power synchronous preamble data line protocol chip design for serial communication is proposed. The serial communication only uses two wires, chip select (CS) and secure digital (SD), to transmit and receive data between two devices. The proposed protocol aims to use a fewer number of wires for the interface, therefore reducing the complexity as well as the area of the chip design. Moreover, it increases the efficiency through a synchronous serial communication-controlled oscillator. The low-power synchronous preamble data line protocol design was successfully verified using a field-programmable gate array (FPGA) as a master device and a real chip as a slave device. The signals are checked through the use of a logic analyzer. The realized low-power synchronous preamble data line protocol chip design has a gate count of only 5.07 K gates, a low power dissipation of 12 mW, and a chip area of 453,260 μm2 using the Taiwan semiconductor manufacturing company (TSMC) 0.18 μm CMOS process. Compared with the three-wire serial peripheral interface (SPI) protocol, the proposed design has the advantages of having a lower cost and a lower power consumption.

Analysis and design of a new low‐phase noise and Gm‐enhanced class‐C quadrature VCO

This study presents a new low-power and low-phase noise Colpitts quadrature voltage-controlled oscillator (QVCO). The proposed QVCO contains two differential Colpitts voltage-controlled oscillators (VCOs) that use gain-boosting technique to enhance the negative transconductance and relax start-up condition. Both switching and tail transistors are configured in class-C to improve impulse sensitivity function and phase noise performance of the circuit via better noise modulation function. In addition, flicker noise would be reduced because of the switched-biasing mechanism of tail transistors. Phase noise analysis shows that changing the bias voltage of switching as well as tail transistors can improve the phase noise performance of the core VCO with overlap reduction of the transistors active time. Consequently, due to no extra noisy elements for coupling and class-C biasing of all transistors, low-phase noise quadrature signals are generated. To verify the performance of the proposed technique, post-layout simulation is performed in Taiwan Semiconductor Manufacturing Company (TSMC) of 0.18 μm Radio Frequency-Complementary Metal-Oxide- Semiconductor (RF-CMOS) process at a supply voltage of 1.2 V. Post-layout simulation results show that the phase noise of the proposed QVCO is −120.6 dBc/Hz at 1 MHz offset from 5.73 GHz operation frequency. The total power consumption of the QVCO is 3.1 mW and the tuning range is from 5 to 5.73 GHz.

A 215-F² Bistable Physically Unclonable Function With an ACF of &lt;0.005 and a Native Bit Instability of 2.05% in 65-nm CMOS Process

This article presents a novel class of bistable physically unclonable functions (PUFs) for security-oriented applications. The traditional cross-coupled bistable PUF cell is divided into P-net and N-net, wherein the P-net (N-net) multiplexing acts as the shared head (foot), and the N-net (P-net) duplicating multiple acts as the PUF cell. The proposed PUF was fabricated in a Taiwan Semiconductor Manufacturing Company (TSMC) 65-nm process with full-custom design. It can parallelly generate 128-bit identifications (IDs) in one clock cycle owing to the random access word-level readout framework. The measurement results show that the randomness and uniqueness of the proposed PUF are consistent with those of the state-of-the-art works. In addition, the proposed PUF has the following features: 1) the PUF cell is composed only of four nMOS transistors with a minimum feature size of 215-F2; 2) the native bit instability at the golden condition (i.e., 1.2 V, 25 °C) with 500 evaluations is only 2.05%, showing a desirable native stability against supply noise; 3) the bit-error-rate dependences of the voltage and temperature are 3.35%/V and 0.011%/°C, respectively, with the voltage varying within the range 1.0–1.4 V and the temperature varying within the range −40 °C to 125 °C; 4) an autocorrelation function of 0.0049 at a 95% confidence level is achieved and is the lowest reported value to date; and 5) the energy efficiency and throughput at the maximum operating frequency (i.e., 433 MHz) are 99.48 fJ/b and 55.5 Gb/s, respectively.

New mixed‐mode second‐generation voltage conveyor based first‐order all‐pass filter

A new plus-type second-generation voltage conveyor (VCII+) based first-order mixed-mode (MM) all-pass (AP) filter is proposed in this study. The proposed MM AP filter employs two VCII+s, three resistors and one grounded capacitor. It has low input and high output impedances for the current-mode selection while it has low input and low output impedances for the transimpedance-mode selection. The AP filter gain is unity for the current output while it is adjustable for the voltage output via a grounded resistor. However, a single passive component matching condition is needed for the proposed MM AP filter. Complete non-ideal analysis by taking into account all the parasitic resistors and non-ideal gains of the VCII+ is performed. The presented theory is verified through SPICE simulations by using supply voltage of ± 0.9 V and 0.18 μm Taiwan Semiconductor Manufacturing Company complementary metal oxide semiconductor technology parameters.

High Gain and High Bandwidth Fully Differential Difference Amplifier as Current Sense Amplifier

A current sense amplifier (CSA) based on a fully differential difference amplifier (FDDA) is introduced. A prototype was manufactured in a 0.18- $\mu \text{m}$ bipolar, CMOS, DMOS (BCD) technology of Taiwan Semiconductor Manufacturing Company, Limited (TSMC) and characterized. The FDDA architecture offers several benefits regarding gain, bandwidth (BW), and noise performance and is well-suited for low-side phase-current measurement (PCM) in modern electric engines. To achieve a high gain accuracy, an integrated resistive feedback, which offers a low-frequency gain of more than 46 dB with a gain error of less than 1% and a 3-dB BW of approximately 2 MHz simulated and confirmed by measurements, is used. Hence, the circuit offers a higher measurement speed and sensitivity than the current state-of-the-art devices. Furthermore, the manual offset reduction allows for an input offset in the low microvolt range, and the input-referred noise is reduced to an input noise voltage of less than $30~\mu \text{V}$ (rms) and a noise floor of ${13}\mathrm {nV} {/\surd } \mathbf {Hz}$ (above 30 kHz). This article describes the design including the top-level structure, the distinct gain stages, the common-mode feedback (CMFB) and the output buffer amplifier of the CSA in detail. Finally, a measurement with a noisy rectangular 1-mV, 500-kHz signal proves the great potential of the amplifier for low-side PCM which is further compared with the state-of-the-art commercial products and research results.

Predictive Modeling for Estimating the Limits for Nonpersistent Effects in MOSFET Response Under Large Signal Gate Injection

In this article, we focus on developing predictive upset models to characterize the nonpersistent effects of large-signal gate-side injection on n-type and p-type metal-oxide semiconductor field-effect transistors ( mosfet s). By “nonpersistent,” we refer to a set of conditions that do not affect the physical characteristics of the device or exhibit any memory effects, i.e., the device will operate normally once the injected large signal stimulus is removed. We present predictive models that determine the maximum limits for large-signal gate-side injection in terms of the device's I ON/ I OFF ratio prior to degradation or damage to the device. A function based on the mosfet technology device parameters, such as its threshold voltage and its power supply rating, is developed and presented. We then validate our predictive models against experimentally measured data for complementary metal–oxide–semiconductor (CMOS) mosfet devices fabricated using 350, 180, 130, and 65 nm standard Taiwan Semiconductor Manufacturing Company (TSMC) CMOS processes. Based on our validated predictive models, we show how the maximum limits for large-signal gate-side injection at 10-MHz change with technology scaling, from ∼9.7 dBm for 350 nm to ∼−1.7 dBm for 65-nm technology nodes for n-type mosfet s; and, from ∼11.0 dBm for 350 nm down to ∼1.2 dBm for 65-nm technology nodes for p-type mosfet s. We anticipate that our predictive models can be leveraged by CMOS circuit designers and electromagnetic interference/compatibility (EMI/EMC) engineers as quick “rule of thumb” guidelines to estimate device and circuit level susceptibility for the injected large signals.

1-W, High-Gain, High-Efficiency, and Compact Sub-GHz Linear Power Amplifier Employing a 1:1 Transformer Balun in 180-nm CMOS

This letter presents a fully integrated two-stage monolithic microwave integrated circuit (MMIC) power amplifier (PA) with a 1:1 transformer balun in Taiwan Semiconductor Manufacturing Company (TSMC) 180-nm CMOS process. To optimize the performance of PA, an on-chip 1:1 turn spiral transformer balun (STB) was used with a high supply power through the cascode topology. The proposed PA achieved a 40-43-dB gain and a saturation power (P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sat</sub> ) of 29.9-30.3 dBm with a 40%-45% of power-added efficiency (PAE) in the frequency range of 820-1000 MHz. Using the antiphase biasing technique, the PA achieves a linear output power of 25 dBm with 29.5% PAE in 20-MHz spacing two-tone measurement, which satisfies IMD3 <; -25 dBc. The measured 1-dB compression point was 28.1 dBm. Furthermore, the proposed PA occupied a core area of 3.3 × 0.86 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

A Current-Injection Class-E Power Amplifier

A novel class-E power amplifier (PA) using a current-injection (CI) technique is presented in this letter. An auxiliary current source, which injects the current into the load during each turn-off period of switching transistors, is introduced into the conventional class-E PA. Without the need of impedance transforming or increasing of the supply voltage, the proposed PA provides a new method to increase the output power. The proposed circuit is fabricated in a Taiwan Semiconductor Manufacturing Company's (TSMC's) 65-nm low power (LP) CMOS process. Measurement results show that the output power of the injected circuit reaches up to 14.12 dBm with a drain efficiency of 41% at 1.8 GHz. The output power improves more than 3 dB compared to the conventional class-E PA without CI.

A Power Analysis Attack Resistant Multicore Platform With Effective Randomization Techniques

Aimed at improving the resistance against power analysis attacks, a systematic and architectural design approach for multicore processors is proposed in this article and is demonstrated in an eight-core prototype platform with low performance overhead and hardware cost. In order to introduce randomness in both the time dimension and the amplitude dimension and make realignment extremely difficult, the proposed multicore platform leverages several methods together, such as random task scheduling (RTS), random insertion of operations (RIO), and frequency and phase randomization (FPR). Moreover, a power state monitoring and control (PSMC) scheme is proposed to defend against power analysis attacks by keeping enough background noises. A test chip of the proposed multicore processor is fabricated in Taiwan Semiconductor Manufacturing Company (TSMC) 65-nm CMOS LP technology and can operate at up to 800 MHz with a 1.2-V supply. The Advanced Encryption Standard (AES) algorithm with these randomization methods is implemented on the processor. Measurement results show that the correlation power analysis (CPA) attacks and the power analysis attacks based on convolutional neural networks (CNNs) are unsuccessful even with 2 000 000 power traces when all the countermeasures are used.

Spintronics: Future Technology for New Data Storage and Communication Devices

Spintronics is a promising technology which aims to solve the major problems existing in today’s conventional electronic devices. Realistically, this technology has the ability to combine the main functions of the modern semiconductor microelectronics and magnetic storage devices in single chip. Electrons have two fundamental degrees of freedom (DOF) called charge and spin. Conventional electronic devices used only the charge of electron for information processing using binary bits 0 and 1. The continuous developments in the conventional electronics are basically depending on reducing component size (transistors, capacitors, etc.) embedded in integrated circuits (random access memory, microprocessor, etc.). In 2019, the actual size of the transistor placed in commercial microprocessor is about 50 nm with gate length of 20 nm and node of 7 nm fabricated using TSMC’s 7-nm FinFET (Taiwan Semiconductor Manufacturing Company 7-nm Fin Field Effect Transistor). The progress in the electronic devices will come to the end when the transistor node size reaches to 1 nm. Below this size, the fabrication, writing, and reading processes will be difficult or impossible due to quantum size effect. Spintronics is the alternative future technology, which is based on using the fundamental spin of electron in additions to its charge to carry and store information. Transfer from conventional electronics to spintronics technology opens the possibilities to construct devices with high storage density, low power consummation, and fast operation and that are cheap and robust. The main aim of this work is to give a simple and clear picture to researchers who are beginners of research in this field. In this review, basic outlines of spintronics technology and its fundamental properties were discussed. Here, we highlight two groups of materials strongly candidates to fabricate spintronics devices, denoted diluted magnetic semiconductor and multiferroic materials.

DESIGN AND MODELING OF A TRIPLE-STEPPED BEAM WITH OUT-OF-PLANE MOTION FOR BISTABLE MICROSWITCH APPLICATIONS

Microswitches have been used for many different applications in building, automation, and security due to requiring little force. A novel design of a triple-stepped beam structure for a mechanical bistable microswitch is presented, and it was found that the bistability of the beam can be achieved by applying an electrostatic force which allows a high deflection with small electrode separation. A finite element method analysis has been used to design the bistable microswitch in a certain range of geometries based on the standard of Taiwan Semiconductor Manufacturing Company (TSMC). The simulation results show that the device requires a verylow input force to get to the bistable stages. The maximum force and the minimum force for switching between the bistable stages are 0.85 mN and 0.23 mN, respectively, which is suitable for electrostatic force at a microscale. The bistability is obtained with the second equilibrium at 75.17 µm that guarantees the perfect contact location between the beam and the conduction path (N+) located at 65.45 µm.

MOSFET‐C ‐based grounded active inductors with electronically tunable properties

In this study, two new grounded metal oxide semiconductor field effect transistor (MOSFET)-C active inductors (AIs) are proposed. The proposed AIs contain only eight MOS transistors and a single grounded capacitor that is attractive for integrated circuit fabrication. Inductance values of them can be electronically tuned by a single control voltage. They do not include any current sources. Therefore, the designs of the proposed AIs are simple and useful. They do not suffer from body effects. Hence, they can be designed with low power supply voltages. Simulation results by using the Cadence analog environment program with 180 nm Taiwan Semiconductor Manufacturing Company (TSMC) nm technology parameters are carried out to indicate the performance of them. Layouts of both proposed AIs occupy the same area of about 78 μm × 78 μm. Postlayout simulation results are given to confirm the validity of the theoretical analysis.

A Low Complexity, High Throughput DoA Estimation Chip Design for Adaptive Beamforming

Direction of Arrival (DoA) estimation is essential to adaptive beamforming widely used in many radar and wireless communication systems. Although many estimation algorithms have been investigated, most of them focus on the performance enhancement aspect but overlook the computing complexity or the hardware implementation issues. In this paper, a low-complexity yet effective DoA estimation algorithm and the corresponding hardware accelerator chip design are presented. The proposed algorithm features a combination of signal sub-space projection and parallel matching pursuit techniques, i.e., applying signal projection first before performing matching pursuit from a codebook. This measure helps minimize the interference from noise sub-space and makes the matching process free of extra orthogonalization computations. The computing complexity can thus be reduced significantly. In addition, estimations of all signal sources can be performed in parallel without going through a successive update process. To facilitate an efficient hardware implementation, the computing scheme of the estimation algorithm is also optimized. The most critical part of the algorithm, i.e., calculating the projection matrix, is largely simplified and neatly accomplished by using QR decomposition. In addition, the proposed scheme supports parallel matches of all signal sources from a beamforming codebook to improve the processing throughput. The algorithm complexity analysis shows that the proposed scheme outperforms other well-known estimation algorithms significantly under various system configurations. The performance simulation results further reveal that, subject to a beamforming codebook with a 5° angular resolution, the Root Mean Square (RMS) error of angle estimations is only 0.76° when Signal to Noise Ratio (SNR) = 20 dB. The estimation accuracy outpaces other matching pursuit based approaches and is close to that of the classic Estimation of Signal Parameters Via Rotational Invariance Techniques (ESPRIT) scheme but requires only one fifth of its computing complexity. In developing the hardware accelerator design, pipelined Coordinate Rotation Digital Computer (CORDIC) processors consisting of simple adders and shifters are employed to implement the basic trigonometric operations needed in QR decomposition. A systolic array architecture is developed as the computing kernel for QR decomposition. Other computing modules are also realized using various linear systolic arrays and chained together seamlessly to maximize the computing throughput. A Taiwan Semiconductor Manufacturing Company (TSMC) 40 nm CMOS process was chosen as the implementation technology. The gate count of the chip design is 454.4k, featuring a core size of 0.76 mm 2 , and can operate up to 333 MHz. This suggests that one DoA estimation, with up to three signal sources, can be performed every 2.38 μs.

Area Efficient High-Performance Digitally Controlled Power Management Unit

Power management unit (PMU) is commonly used to manage power modules to achieve high efficient performance for integrated circuits. Inside the PMU, controllers that belong to different power modules could be pretty much similar. If the discrete feature of the digital control can be gainfully arranged, we can use only one controller to operate all the power modules inside the PMU, which can reduce circuit area and save cost. This article proposes a pipeline concept to realize this idea. To achieve high performance, this article also introduces a phase sequence interchange technique to reduce the cross regulation problem of the single inductor dual outputs converter and an autotuning charge balance algorithm (AT-CBA) to enhance the transient response. The PMU is fabricated in Taiwan Semiconductor Manufacturing Company (TSMC) 0.18 μm CMOS manufacturing process for functional validation. Experimental results show that the pipeline controlled PMU can simultaneously output six voltages with extremely low cross regulation. The proposed AT-CBA also successfully make both buck converter and low-dropout achieve near-optimal transient response in 40 mV/5 μs and 120 mV/1 μs, respectively.

Low power and area efficient error tolerant adder for image processing application

SummaryApproximate computing‐based arithmetic units are oriented towards reduction in power, delay, and area. Intrinsic error tolerance capability of emerging application domains, like multimedia, Internet of Things (IoT), and image processing provides better opportunities for optimization of approximate arithmetic units. In this paper, a novel 1‐bit imprecise full adder (IFA) is proposed with less gate count. Also, two versions of 16‐bit error tolerant adders (ETAs), namely a low power and area efficient error tolerant adder (LETA) and improved low power and area efficient error tolerant adder (ILETA), are proposed. In these proposed ETAs, the most significant bit (MSB) segments are realized in same approach, whereas the least significant bit (LSB) segment of LETA and ILETA are realized using an existing modified full adder (MFA) and proposed IFAs, respectively. The proposed and existing ETA adders are implemented using a Verilog hardware description language (HDL) and synthesized in a Synopsys electronic design automation (EDA) Tool using Taiwan Semiconductor Manufacturing Company (TSMC) 65nm technology. The proposed (ILETA, LETA) adders exhibit (55%, 50%) reduction in power consumption and achieve significant reduction in area (68%, 61%). Further, in this work, a new performance metric namely power and error product (PEP) is proposed in order to evaluate the approximate adders in terms of power and error metrics. It is found that the proposed ILETA achieves a low PEP of 1.05 compared with other ETAs. To study the efficacy of the proposed ETA adders in image processing application, an image blending algorithm is implemented and simulated using MATLAB. From simulation results, it is observed that the proposed ETA adders exhibit a high peak signal‐to‐noise ratio (PSNR).

A 45 nm CMOS Avalanche Photodiode with 8.4-GHz Bandwidth

Photodiode is one of the key components in optoelectronic technology, which is used to convert optical signal into electrical ones in modern communication systems. In this paper, an avalanche photodiode (APD) is designed and fulfilled, which is compatible with Taiwan Semiconductor Manufacturing Company (TSMC) 45-nm standard complementary metal–oxide–semiconductor (CMOS) technology without any process modification. The APD based on 45 nm process is beneficial to realize a smaller and more complex monolithically integrated optoelectronic chip. The fabricated CMOS APD operates at 850 nm wavelength optical communication. Its bandwidth can be as high as 8.4 GHz with 0.56 A/W responsivity at reverse bias of 20.8 V. Its active area is designed to be 20 × 20 μm2. The Simulation Program with Integrated Circuit Emphasis (SPICE) model of the APD is also proposed and verified. The key parameters are extracted based on its electrical, optical and frequency responses by parameter fitting. The device has wide potential application for optical communication systems.

4th-Order Switched-Current Multistage-Noise-Shaping Delta-Sigma Modulator With a Simplified Digital Noise-Cancellation Circuit

This paper proposes a fourth-order (2-2) switched-current (SI) multistage-noise-shaping (MASH) delta-sigma modulator (DSM) with a simplified digital noise-cancellation circuit (DNCC) by using a Taiwan Semiconductor Manufacturing Company (TSMC) 0.18 μm 1P6M CMOS process. In view of area efficiency, we propose a small-area current-mode sample-and-hold circuit (S/H) with a modified feedback memory cell (FMC) and cross-connected bias circuit. As a result of modifications to the feedback impedance, the input impedance of the current-mode differential FMC was decreased by [2 + (g' <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m3</sub> /g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m1</sub> - 1) x A] times relative to a traditional FMC. Any input current can be processed faster than usual given low input impedance. The MASH architecture inherited a superior signal-to-noise ratio (SNR) due to a simplified DNCC, consisting of six unit-delay circuits using a master-slave D flip-flop (DFF) and a logic circuit using a Karnaugh map. Post-layout simulations reveal that the simulated SNR was 87.1 dB and the effective number of bits (ENOB) was 14.18 bits. Measurements indicated that the SNR was 64.5 dB and the ENOB was 10.42 bits-at a sampling frequency of 10.24 MHz, an oversampling ratio of 256, a signal bandwidth of 20 kHz, and a supply voltage of 1.8 V. The designed chip was measured to have a power consumption of 18.19 mW, a chip area of 0.13 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , and a measured figure of merit (FoM) of 331.9 (pJ/conv-step). The advantages of our modulator are its small chip area and high processing speed at all input currents.

New analogue stop‐learning control module using astrocyte for neuromorphic learning

Learning algorithms and devices are an essential part of neural networks and neuromorphic architectures. Astrocyte, as an important element in the learning of neural networks, is believed to play a key role in long-term synaptic plasticity and memory. In addition, recent experimental observations indicate that astrocytes are active elements in learning in complex networks. In this study, the authors propose a new analogue astrocyte circuit that consumes fewer numbers of transistors compared to its previous counterparts. The authors then use this astrocyte to design a novel analogue circuit to implement a stop-learning mechanism in a spike-based learning algorithm and present its neuromorphic very large scale integration (VLSI) simulations. Experimental results demonstrate that the designed circuit can precisely implement the learning mechanisms shown by previous studies implementing spike-based learning rules without astrocyte. The proposed circuit proposes the first analogue stop-learning control algorithm that uses astrocytes. It has been designed and simulated in Taiwan semiconductor manufacturing company (TSMC) 0.35 μm complementary metal-oxide semiconductor (CMOS) technology.