System-level Power Research Articles

TinyRadarNN: Combining Spatial and Temporal Convolutional Neural Networks for Embedded Gesture Recognition With Short Range Radars

This work proposes a low-power high-accuracy embedded hand-gesture recognition algorithm targeting battery-operated wearable devices using low-power short-range RADAR sensors. A 2-D convolutional neural network (CNN) using range-frequency Doppler features is combined with a temporal convolutional neural network (TCN) for time sequence prediction. The final algorithm has a model size of only 46 thousand parameters, yielding a memory footprint of only 92 KB. Two data sets containing 11 challenging hand gestures performed by 26 different people have been recorded containing a total of 20'210 gesture instances. On the 11 hand gesture data set, accuracies of 86.6% (26 users) and 92.4% (single user) have been achieved, which are comparable to the state of the art, which achieves 87% (10 users) and 94% (single user), while using a TCN-based network that is 7500× smaller than the state of the art. Furthermore, the gesture recognition classifier has been implemented on a parallel ultralow power processor, demonstrating that real-time prediction is feasible with only 21 mW of power consumption for the full TCN sequence prediction network, while a system-level power consumption of less than 120 mW is achieved. We provide open-source access to example code and all data collected and used in this work on tinyradar.ethz.ch.

Computational Cost Analysis and Data-Driven Predictive Modeling of Cloud-Based Online-NILM Algorithm

Online non-intrusive load monitoring algorithms have captivated academia and industries as parsimonious solutions for household energy efficiency monitoring as well as a safety control, anomaly detection, and demand-side management. However, the computational energy cost for executing such algorithms should not overcome the promised energy efficiency from the disaggregated appliance specific consumption information feed-backs. Moreover, the energy efficiency of cloud computing systems is also becoming a concern for the environment due to carbon emission. This study analyzes the energy spent to execute NILM algorithms via computation cost estimation and prediction using computing system-level power monitoring and data-driven approaches. A generic framework for an automated algorithm cost monitoring and modeling methodologies is devised for large load scale deployment of Cloud-based Online-NILM algorithms. The efficacy of the proposed approach was examined and validated on two computing system use-cases, i.e., Dedicated Server and Cloud Virtual Server. The prediction models, developed using statistical and machine learning tools, demonstrate the promising applicability of the data-driven approach with a very high prediction accuracy without detailed knowledge of the computing systems and the algorithm.

External vs. Integrated Light Sources for Intra-Data Center Co-Packaged Optical Interfaces

Co-packaging of optics and electronics for data center switches has been proposed to reduce system-level power consumption by minimizing power-hungry electrical interconnects. Co-packaging optical components near high-temperature electronics, however, can diminish their performance and reliability. Moreover, limitations of the switch environment, such as restricted footprint, power, and number of fiber attachments can limit practical co-packaging implementations. Here, we study four architectures for co-packaged optical interfaces using either single- or multi-wavelength light sources that can be either external to or integrated with the optical interfaces. We model the temperature- and current-dependent performance and reliability of the sources and calculate the link budget for switch bandwidths up to 102.4 Tb/s. We compare architectures based on coherent and direct detection and find that all coherent detection architectures support 102.4 Tb/s switching with over 13 dB link budget, while most direct detection architectures scale to 51.2 Tb/s or 102.4 Tb/s switching with link budgets less than 5 dB. In addition, we demonstrate that external-source architectures require wavelength-division multiplexing at lower switch bandwidths and consequently have link budgets 1-5 dB lower than integrated source architectures. Further, we demonstrate that higher-power lasers can scale external architectures to 102.4 Tb/s switching with over 4 dB link budgets. Finally, for 51.2 Tb/s switching, we show that a reduction in integrated source temperature improves link budgets by 2-4 dB and direct detection external-source architectures can achieve greater than 5 dB link budget with fewer than 300 fiber attachments.

Self-aware power management for multi-core microprocessors

Power management is one of the significant challenges to be addressed in multi-/many-core microprocessors. Furthermore, the multi-core microprocessors experience unforeseen scenarios such as performance degradation over time, manufacturing defects, power, and thermal impacts with time. Traditional power management techniques, though efficient, is not designed to handle such unseen scenarios. Furthermore, the variation in performance requirements is one of the challenges faced in the era of machine learning. We propose a self-aware power management scheme for multi-core microprocessors in this work to address the above-mentioned issues. We perform application-level power management in this work to overcome the overheads imposed by core-level power management and system-level power management inefficiency. The power management unit employs a linear predictor for workload prediction to perform DVFS. On top of the power manager, the self-aware controller is hierarchically placed to monitor the system components’ health and adapt the power manager's decision to meet the performance requirements and handle changes in system components’ health. We evaluate the proposed self-aware power manager under externally provided high performance goals, and resource contention. A power saving of up to 16% compared to existing power management techniques, and 2.4× speedup with 25% additional power to satisfy high performance compared to power management without self-awareness for a microprocessor with up to 32-cores is achieved.

Simultaneous Management of Peak-Power and Reliability in Heterogeneous Multicore Embedded Systems

Analysis of reliability, power, and performance at hardware and software levels due to heterogeneity is a crucial requirement for heterogeneous multicore embedded systems. Escalating power densities have led to thermal issues for heterogeneous multicore embedded systems. This paper proposes a peak-power-aware reliability management scheme to meet power constraints through distributing power density on the whole chip such that reliability targets are satisfied. In this paper, we consider peak power consumption as a system-level power constraint to prevent system failure. To balance the power consumption, we also employ a Dynamic Frequency Scaling (DFS) method to further reduce peak power consumption and satisfy thermal constraints on the chip. We illustrate the benefits of our scheme by comparing it with state-of-the-art schemes, resulting in average in 26.5 percent less peak power consumption (up to 54.3 percent).

Accurate Energy Modelling of Hybrid Parallel Applications on Modern Heterogeneous Computing Platforms Using System-Level Measurements

Modern high-performance computing platforms, cloud computing systems, and data centers are highly heterogeneous containing nodes where a multicore CPU is tightly integrated with accelerators. An important challenge for energy optimization of hybrid parallel applications on such platforms is how to accurately estimate the energy consumption of application components running on different compute devices of the platform. In this work, we propose a method for accurate estimation of the application component-level energy consumption employing system-level power measurements with power meters. We experimentally validate the method on a cluster of two hybrid heterogeneous computing nodes using three parallel applications - matrix-matrix multiplication, 2D fast Fourier transform and gene sequencing. The experiments demonstrate a high estimation accuracy of the proposed method, with the average estimation error ranging between 2% and 5%. The average error demonstrated by the state-of-the-art estimation methods for the same experimental setup ranges from 15% to 75%, while the maximum reaches 178%. We also show that the use of the state-of-the-art estimation methods instead of the proposed one in the energy optimization loop leads to significant energy losses (up to 45% in our case).

A Simultaneous Multiband Continuous-Time $\Delta\Sigma$ ADC With 90-MHz Aggregate Bandwidth in 40-nm CMOS

This letter presents a new class of ΔΣ modulator that combines any set of traditional NTF shapes in a single modulator. The prototype multiband ΔΣ modulator (MB-ΔΣM) demonstrates two simultaneous bands - one baseband and one bandpass. These two bands are separated by 500 MHz, have an aggregate bandwidth of 90 MHz, with up to 55-dB measured SNDR. In addition to reducing the number of ADCs, this new approach promises further system-level power savings by simplifying the RF frontend. The system-level power savings from requiring fewer analog mixers, LNAs, filters, and ADC drivers can be even more than the ADC power reduction.

Meeting Thermal Safe Power in Fault-Tolerant Heterogeneous Embedded Systems

Due to the system-level power constraints, it is encountered that not all cores in a multicore chip can be simultaneously powered-on at the highest voltage/frequency levels. Also, in the future technology nodes, reliability issues due to the susceptibility of systems to transient faults should be considered in multicore platforms. Therefore, two major objectives in designing multicore embedded systems are low energy/power consumption and high reliability. This letter presents an energy management system that optimizes the energy consumption such that it satisfies reliability target and meets timing, thermal design power (TDP) and thermal safe power (TSP) constraints. Toward the TDP/TSP-constrained energy-reliability optimization, the proposed method schedules periodic real-time applications on different types of cores with voltage/frequency variations for heterogeneous multicore embedded systems. Experiments show that our proposed system provides up to 38.19% (in average by 29.66%) energy saving and up to 54.73% peak power reduction (in average by 24.55%) under different reliability targets and TDP/TSP constraints when compared to the state-of-the-art techniques.

Optimal Charging and Discharging Control of Plug-in Hybrid Electric Vehicles in a System-level Power Distribution Network

With the increasing popularity of plug-in hybrid electric vehicles (PHEVs), coordinated charging and discharging of PHEVs has become an important issue in power distribution networks. To this end, we employ a multi-objective optimization model to formulate the problem of coordinated charging and discharging of PHEVs, in which the objectives of load shifting and total costs minimization are both investigated under system’s technical constraints. A hierarchical optimal algorithm combining the iterative water-filling-based algorithm and the consensus-based method is proposed to solve the multi-objective optimization problem. It shows that the proposed algorithm not only enhances stable performance for the power load but also guarantees low-cost satisfaction for the vehicle owners in the system-level power distribution network integrating physical power network with information network together. Numerical simulations are presented to demonstrate the effectiveness of the proposed algorithm.

Physics-Based Circuit Modeling Methodology for System Power Integrity Analysis and Design

A physics-based circuit modeling methodology for system-level power integrity (PI) analysis and design is presented herein. The modeling methodology is based on representing the current paths in the power distribution network (PDN) with appropriate circuits based on cavity model and plane-pair partial element equivalent circuit (PEEC). The PDN input impedance looking from on-chip sources can be computed. A commercial simulation tool is used to corroborate the modeling approach where the system consists of a commercial integrated circuits, a complex organic package and a very high-layer-count printed circuit board. Two types of circuit models are proposed from the methodology with physical correspondence maintained in the circuit elements. The circuits can be used to analyze the geometry impact on the PDN impedance and explore design improvements. Voltage ripple simulations are conducted with the circuit models. The simulated results correlated with measurements. The modeling methodology helps to understand the impact of the fundamental physics of the different parts of the PDN system and the impact of changes in the PI designs.

A feasibility study on integrating large-scale battery energy storage systems with combined cycle power generation – Setting the bottom line

Strong attention has been given to the costs and benefits of integrating battery energy storage systems (BESS) with intermittent renewable energy systems. What's neglected is the feasibility of integrating BESS into the existing fossil-dominated power generation system to achieve economic and environmental objectives. In response, a life cycle cost-benefit analysis method is introduced in this study taking into consideration three types of battery technologies, namely, vanadium redox flow battery, zinc bromine flow battery, and lithium-iron-phosphate battery. The objective is to evaluate the life cycle carbon emissions and cost of electricity production by combined cycle power generation with grid-connected BESS. Findings from the Singapore case study suggest a potential 3–5% reduction in the life cycle carbon emission factors which could translate to a cumulative carbon emission reduction of 9–16 million tonnes from 2018 to 2030 from electricity generation. Grid-connected BESS could reduce the levelized cost of electricity by 4–7%. A synergistic planning of CCGT and BESS could theoretically reduce the system level power generation capacity by 26% albeit a potential increase in the overall capital cost at the current cost of batteries. The projected battery cost reduction is critical in improving the feasibility of large-scale deployment.

Low-power and high-performance adaptive routing in on-chip networks

Performance and power are two conflict requirements in a NoC. It is attractive to propose a low-power and high-performance routing scheme. A new low-power fully adaptive routing algorithm is proposed for virtual cut-through or wormhole switched networks-on-chip. The following new techniques are proposed: (1) multiple packets can be delivered across the same physical channel via different bypassing channels, (2) a low-power bypassing hop can include both x and y channels, (3) a new low-power routing selection function is defined for more power reduction, (4) a new limited-global control signaling scheme is proposed, (5) a new cycle-accurate system-level power estimation model is proposed, and (6) bypassing hops of any lengths and the normal hops in the original network can share the same virtual channels. Simulation results are presented to evaluate the performance and power by comparison with some previous methods.

Multi-Tb/s-per-Fiber Coherent Co-Packaged Optical Interfaces for Data Center Switches

Co-packaging of optical and electronic interfaces inside data center switches has been proposed to reduce the system-level power consumption and support higher density, higher capacity optical links. However, co-locating electronics and optics increases optical losses and exposes lasers, (de)multiplexers and other components to temperature fluctuations. We propose a design for co-packaged interfaces using coherent detection and wide-passband (de)multiplexers to increase the total bit rate per fiber in the presence of demultiplexer center frequency shifts up to ±150 GHz. We compare direct and coherent detection systems within this architecture and demonstrate that unamplified coherent links can provide over 20 dB higher loss budget than direct detection links at 400 Gb/s per fiber. Moreover, coherent links can offer far higher bit rates per fiber. For example, in the presence of (de)multiplexer center frequency shifts of up to ±150 GHz, DP-QPSK links can scale to over 5 Tb/s per fiber, while four pulse amplitude modulation (PAM) links are optical bandwidth limited to ~400 Gb/s per fiber. We quantify signal path loss and optical signal-to-noise ratio budgets when optical amplifiers, limited to eye-safe output powers, are used to compensate for losses of fibers or optical switches. While the loss and SNR budgets of direct detection links may be improved by optical amplifiers, these systems cannot scale to high bit rates per fiber because large channel spacings are required to accommodate (de)multiplexer center frequency shifts. For example, amplified 4-PAM links can scale to less than 1.3 Tb/s per fiber, while amplified DP-QPSK links can scale to greater than 12.8 Tb/s per fiber.

Design route towards a PM machine for rotorcraft environments

This paper discusses the design route followed in the development of a permanent magnet (PM) machine for electrical power generation on board a rotorcraft (helicopter). The focus of the machine design is to optimise system power density, efficiency, and robustness – all of which are crucial considerations in aerospace applications. A matrix of designs was created consisting of two stators with different winding conductors – copper and aluminium – and three rotors, each using different containment sleeve materials. These include two semi-permeable metallic sleeves, which act to decrease the effective air gap. Combinations of the different materials will yield different system-level power densities and efficiencies. Here, all the designs are presented along with the initial test results for the baseline machine combination validating the design predictions.

System-Level Power Delivery Network Analysis and Optimization for Monolithic 3-D ICs

As 2-D scaling reaches its limit, monolithic 3-D (M3D) IC is a leading contender for continuing equivalent scaling. Although M3D shows power and performance benefits over 2-D designs, designing a power delivery network (PDN) for M3D is challenging. In this paper, for the first time, we present a system-level PDN model of M3D designs focusing on both resistive (IR) and inductive ( $\text{L}di/dt$ ) components of power supply integrity. In addition, we present frequency- and time-domain analyses of M3D PDNs. We show that the additional resistance in M3D PDNs, while being worse for resistive drops, improves resiliency against ac current noise showing 35.9% peak impedance reduction compared to 2-D PDNs during worst case resonant oscillations. Then, we present methodologies to improve power supply integrity of M3D designs based on the observations. Our optimization methodologies offer up to 32.6% and 17.0% static and dynamic voltage drop reduction compared to the baseline M3D designs, respectively, showing 9.0% lower dynamic voltage drop compared to the 2-D counterparts.

Fast and Accurate System-Level Power Estimation Model for FPGA-Based Designs

In this paper, we present an efficient and fast system-level power estimation model for the FPGA-based designs. To estimate the dynamic power early, first time, LLVM IR code analysis is employed at the C-level designs and then the neural network-based estimation model is built from the information obtained from this high-level profiling. The model accuracy is validated through designs of heterogeneous domains from the CHStone and MachSuite benchmarks. An insignificant relative error of 0.21–3.6% is observed for the analyzed benchmark designs with the exceptional increase in the estimation speed by 63 times of magnitude as compared to the Xilinx Vivado Design Suite. Moreover, the model eliminates the need for synthesis-based exploration. In addition, the effectiveness of proposed approach is also verified through a comparison with the other reported works.

Dynamic Sensor-Frontend Tuning for Resource Efficient Embedded Classification

Emerging portable applications, including human activity recognition and robot navigation, require always-on sensing technologies to continuously monitor the environment. Continuous sensing, however, strongly dominates the hardware devices’ power consumption and consequently hampers the systems’ always-on functionality. In this paper, we propose a circuit-aware machine learning scheme that exploits the devices’ ability to dynamically tune the quality of its sensors to trade-off system level accuracy versus total system-level power consumption. To this end, we: 1) analytically derive the power-quality trade-off space in sensory front-ends; 2) use these equations to make the probabilistic relations between sensory features and their degraded versions explicit in a Bayesian network classifier; and 3) propose a methodology building upon this model to control the required sensory information quality at run-time. We show how this enables to tune the circuit’s power consumption versus inference accuracy trade-off space with fine granularity, and achieve significant power savings at almost no accuracy loss. In addition, our methodology is able to cope with sensor failure and with a dynamically changing environment by means of an efficient on-line tuning strategy. This dynamic power-vs-quality scalability is empirically shown on various machine learning benchmarking data sets.

Power Optimization in System Level Using Profiling Technique

Power optimization has become an essential and major source of concern at the system level design. With the shrink in transistor length and the attractiveness of handy electronic devices, power dissipation has become a serious issue. System level power optimization technique gains more popularity since many techniques can be applied in reduction of power. Although, there are numerous techniques to reduce power dissipation, simpler methods has not been implemented on a system level. In this paper we use profiling technique, a process which helps one to know which portion of the function takes more time compared to other during the simulation. The portion which takes large time for simulation is port mapped to the FPGA while the rest is assigned to the processor. By this technique we can see considerable amount of power savings.

A Survey of System Level Power Management Schemes in the Dark-Silicon Era for Many-Core Architectures

Power consumption in Complementary Metal Oxide Semiconductor (CMOS) technology has escalated to a point that only a fractional part of many-core chips can be powered-on at a time. Fortunately, this fraction can be increased at the expense of performance through the dark-silicon solution. However, wi

A Pitch-Matched Front-End ASIC With Integrated Subarray Beamforming ADC for Miniature 3-D Ultrasound Probes

This paper presents a front-end application-specified integrated circuit (ASIC) integrated with a 2-D PZT matrix transducer that enables in-probe digitization with acceptable power dissipation for the next-generation endoscopic and catheter-based 3-D ultrasound imaging systems. To achieve power-efficient massively parallel analog-to-digital conversion (ADC) in a 2-D array, a 10-bit 30 MS/s beamforming ADC that merges the subarray beamforming and digitization functions in the charge domain is proposed. It eliminates the need for costly intermediate buffers, thus significantly reducing both power consumption and silicon area. Self-calibrated charge references are implemented in each subarray to further optimize the system-level power efficiency. High-speed datalinks are employed in combination with the subarray beamforming scheme to realize a 36-fold channel-count reduction and an aggregate output data rate of 6 Gb/s for a prototype receive array of $24 \times 6$ elements. The ASIC achieves a record power efficiency of 0.91 mW/element during receive. Its functionality has been demonstrated in both electrical and acoustic imaging experiments.