Meeting Thermal Safe Power in Fault-Tolerant Heterogeneous Embedded Systems

Abstract

Due to the system-level power constraints, it is encountered that not all cores in a multicore chip can be simultaneously powered-on at the highest voltage/frequency levels. Also, in the future technology nodes, reliability issues due to the susceptibility of systems to transient faults should be considered in multicore platforms. Therefore, two major objectives in designing multicore embedded systems are low energy/power consumption and high reliability. This letter presents an energy management system that optimizes the energy consumption such that it satisfies reliability target and meets timing, thermal design power (TDP) and thermal safe power (TSP) constraints. Toward the TDP/TSP-constrained energy-reliability optimization, the proposed method schedules periodic real-time applications on different types of cores with voltage/frequency variations for heterogeneous multicore embedded systems. Experiments show that our proposed system provides up to 38.19% (in average by 29.66%) energy saving and up to 54.73% peak power reduction (in average by 24.55%) under different reliability targets and TDP/TSP constraints when compared to the state-of-the-art techniques.