Fast and Accurate System-Level Power Estimation Model for FPGA-Based Designs

Abstract

In this paper, we present an efficient and fast system-level power estimation model for the FPGA-based designs. To estimate the dynamic power early, first time, LLVM IR code analysis is employed at the C-level designs and then the neural network-based estimation model is built from the information obtained from this high-level profiling. The model accuracy is validated through designs of heterogeneous domains from the CHStone and MachSuite benchmarks. An insignificant relative error of 0.21–3.6% is observed for the analyzed benchmark designs with the exceptional increase in the estimation speed by 63 times of magnitude as compared to the Xilinx Vivado Design Suite. Moreover, the model eliminates the need for synthesis-based exploration. In addition, the effectiveness of proposed approach is also verified through a comparison with the other reported works.