Switched Capacitor Array Research Articles

A 30–36 GHz Passive Hybrid Phase Shifter With a Transformer-Based High-Resolution Reflect-Type Phase Shifting Technique

This brief presents a passive hybrid phase shifter consisted of a 5-bit switch-type phase shifter (STPS) and a 4-bit high resolution reflection-type phase shifter (RTPS). The STPS as the main body of the circuit utilizes the bridged T-type and high-pass/low-pass phase shifting cells. A novel high-resolution RTPS is proposed as a supplement of the STPS to improve the phase resolution and minimize the phase error. In the RTPS, a novel reflective load, which contains a transformer and a 4-bit digital-controlled switched capacitor array, is adopted. The transformer in the RTPS can weaken the variation of the reflection coefficient resulted by a large-capacitance switched capacitor array, which makes the control of the phase shifting more convenient and accurate at millimeter-wave (mm-wave) frequency. A proof-of-concept prototype was implemented in 55 nm CMOS technology. Measured results show that the root-mean-square (RMS) phase error of the proposed phase shifter in a step of 2.8° is 0.69 – 2.19° at 30 – 36 GHz, and less than 1.1° from 30 to 34 GHz. An average insertion loss (IL) of 12.6 – 14.6 dB is achieved. The core circuit occupies 0.24 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> without DC power consumption.

Design and first performance results of waveform sampling readout electronics for Large Area Picosecond Photodetector

Large Area Picosecond Photodetectors (LAPPD) are a new generation of microchannel plate photomultipliers being manufactured by Incom. These devices feature large sensitive area of 350 cm2, high quantum efficiency (∼ 20%), and tens of picosecond single photon timing resolution. LAPPDs use an anode structure with 28 striplines, allowing for spatial resolution of 1 ÷ 3 mm while minimizing the number of readout channels. In this report, we present our design of integrated readout electronics for the LAPPD . These electronics read out all 2×28 channels of a stripline-anode LAPPD . Waveform sampling at up to 5GSPS is performed by 8 DRS4 switched-capacitor array ASICs. All DRS4 channels are digitized in parallel with two 32-channel ADCs. An on-board FPGA coordinates digitization and readout of waveforms, and could further be expanded to include some waveform processing. Data packages built in the FPGA are sent to a data acquisition system (DAQ) via optical fiber, with a baseline Gigabit Ethernet interface implemented entirely on the FPGA . The electronics is designed to accommodate different triggering options: self-triggering using DRS4 transparent mode and external triggering, making event control very flexible. Further flexibility is enhanced with embedded software for an on-FPGA soft-core processor, as well as DAQ readout and control software. The device is plug and play with any existing IP network. An open-source ecosystem is being developed to provide full control of the device operation and an easy way to integrate it to any environment. In the report we describe the status of the electronics development, its firmware and readout software. Also the results of the first tests of the electronics with the LAPPD devices will be presented.

A 3.3-mW 25.2-to-29.4-GHz Current-Reuse VCO Using a Single-Turn Multi-Tap Inductor and Differential-Only Switched-Capacitor Arrays With a 187.6-dBc/Hz FOM

A millimeter-wave current-reuse voltage-controlled oscillator (VCO) features a single-turn multi-tap inductor and two separate differential-only switched-capacitor arrays to improve the power efficiency and phase noise (PN). Specifically, a single-branch complementary VCO topology, in conjunction with a multi-resonant Resistor-Inductor-Capacitor-Mutual inductance (RLCM) tank, allows sharing the bias current and reshaping the impulse-sensitivity-function. The latter is based on an area- efficient RLCM tank to concurrently generate two high quality- factor differential-mode resonances at the fundamental and 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nd</sup> - harmonic oscillation frequencies. Fabricated in 65-nm CMOS technology, our VCO at 27.7 GHz shows a PN of -109.91-dBc/Hz at 1-MHz offset (after on-chip divider-by-2), while consuming just 3.3 mW at a 1.1-V supply. It corresponds to a Figure-of-Merit (FOM) of 187.6 dBc/Hz. The frequency tuning range is 15.3% (25.2 to 29.4 GHz) and the core area is 0.116 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

A low‐phase‐noise and low‐power CMOS colpitts VCO using Gm boosting and capacitance switching techniques

AbstractThis letter presents a low‐power and low‐phase‐noise 5‐GHz VCO fabricated in a standard CMOS 0.18‐μm process. The low power dissipation was achieved by using the PMOS cross‐coupled pair and Gm‐boosting topology, and the low phase noise was obtained by adding two pairs of switched capacitor array. The VCO consumed a dc power of 2.92 mW with the supply voltage of 1 V. The measured phase noises were − 104.6 dBc/Hz and − 117.4 dBc/Hz at 1 MHz offset frequency with switched off and on capacitances, respectively, which demonstrated 12.8‐dB improvement.

Design of prototype Front-End Electronics for the Gamma-Gamma collider

The Gamma-Gamma collider is a scientific facility proposed in China to observe two unique interactions at the center-of-mass energy of 1–2 MeV, namely γγ scattering and electron-positron pairs. In the experiment, two γ beams generated by the Compton back-scattering of high-energy electron beams (∼200 MeV) and high-intensity laser beams will collide at the interaction point, and the products will be collected by CsI(Na) crystals and plastic scintillators, and then converted into electric signals by silicon photomultiplier (SiPM) detectors. In this paper, a prototype Front-End Electronics (FEE) is implemented to verify the design requirements concerning the noise level (no more than 3 mV), high sampling rate (1 GS/s) and low power consumption. The prototype FEE comprised 8 differential drivers, 2 low-power switch capacitor array (SCA) DRS4 chips, and an 8-channel Analog-to-Digital Converter (ADC). The input signals were first stored in DRS4 chips for time stretching, then digitized by the ADC, and finally sent to back-end electronics via an optical link. The noise (RMS) of each readout channel on the prototype FEE was less than 3 mV after offset correction, and the ENOB of the channels was better than 6.7 bit when the frequency of input sine waves was less than 70 MHz and the sampling rate of the DRS4 was 1 GS/s. Therefore, the performance of the prototype FEE meets the requirements of the Gamma-Gamma collider.

A Design of Wide-Range and Low Phase Noise Linear Transconductance VCO with 193.76 dBc/Hz FoMT for mm-Wave 5G Transceivers

This paper presents a wide-range and low phase noise mm-Wave Voltage Controlled Oscillator (VCO) based on the transconductance linearization technique. The proposed technique eliminates the deep triode region of the active part of the VCO, and lowers the noise introduced by the gm-cell. The switch sizes inside the switched capacitor bank of the VCO are optimized to minimize the resistance of the switches while keeping the wide tuning range. A new layout technique shortens the routing of the VCO outputs, and lowers the parasitic inductance and resistance of the VCO routing. The presented method prevents the reduction of the quality factor of the tank due to the long routing. The proposed VCO achieves a discrete frequency tuning range, of 14 GHz to 18 GHz, through a linear coarse and middle switched capacitor array, and offers superior phase noise performance compared to recent state-of-the-art VCO architectures. The design is implemented in a 45 nm CMOS process and occupies a layout area (including output buffers) of 0.14 mm2. The power consumption of the VCO core is 24 mW from the power supply of 0.8 V. The post-layout simulation result shows the VCO achieves the phase noise performances of −87.2 dBc/Hz and −113 dBc/Hz, at 100 kHz and 1 MHz offset frequencies from the carrier frequency of 14 GHz, respectively. In an 18 GHz carrier frequency, the results are −87.4 dBc/Hz and −110 dBc/Hz, accordingly.

Offset-free DC-coupled analog frontend circuit for high-dynamic-range signals

The analog frontend (AFE) coupling circuit is a crucial processing element for data acquisition systems based on analog-to-digital converters (ADCs). Currently, high-speed and high-resolution ADCs are predominantly designed with differential input stages. Conventional high-speed ADC drivers are mainly AC-coupled by employing transformers (Baluns) or fully differential amplifiers (FDAs) with blocking capacitors. However, the results of this study indicate that a certain degree of DC offset error exists and manifests itself as the baseline error in the presence of power dividers connecting several DC-coupled channels that implement high-dynamic-range (HDR) signal conditioning. The study involves a theoretical analysis and explanation of the baseline offset error. The offset error can potentially lead to unexpected out-of-range issues for sampling devices, including high-speed ADCs and switched capacitor array ASICs. High-performance FDAs are adopted, and an offset-free DC-coupled AFE circuit is proposed to address the aforementioned issue using two-stage amplification and a resistive attenuator. The proposed methodology is verified via circuit simulations and hardware design. Thus, the baseline offset problem can be accurately solved using the proposed circuit by minimizing the neglectable error. The proposed circuit facilitates improvements in the high-precision measurement of HDR signals in many nuclear physics experiments and some applications in the DC-coupling scheme with FDAs involving resistive power dividers.

Design of a Digital Readout Module for SCA ASIC Testing

Switched Capacitor Array (SCA) features high-speed sampling and low power consumption. High-speed waveform digitization based on SCA is an important research direction for high-precision time measurement. We are designing the SCA ASIC chips, of which several prototypes have been designed and the improvements are ongoing. In order to test and evaluate the future SCA ASIC chips, it is necessary to design a digital readout module with good compatibility. This paper presents the design of the readout module and the data readout software. The digital readout module integrates the functionality of the control, configuration and data readout of the ASIC under test within one FPGA device. A DDR3 chip is used for data caching, and a USB3.0 interface is designed for data transmission. The readout software is designed based on Python3.7 and contains the functions such as data acquisition and waveform drawing. This module was successfully used in the initial testing of the second version of the SCA prototype ASIC, and the test results indicate that the readout module works as expected.

A Wireless Servo Motor Drive With Bidirectional Motion Capability

In this paper, a novel wireless servo motor drive is proposed and implemented, which artfully integrates wireless power transfer into the dc servo motor drive to achieve wireless bidirectional servo motion. Prominently, there is no power converter or controller at the servo motor side to realize the bidirectional rotation, while the motor control is fully conducted at the transmitter side. The key is to adopt only one transmitter with LCL network to achieve power equalization of two receiver coils, hence realizing bidirectional motion. Meanwhile, the phase-shift control method is newly developed to perform the desired speed control at the transmitter side, without requiring any switched capacitor arrays. As a result, the proposed wireless bidirectional servo motor drive takes the definite advantages of electrocution free and totally sealable. Both calculation and experimental results are presented to validate the feasibility and controllability. For the prototype, the transmission distance can reach up to 130 mm and the transmission efficiency can be up to 85%.

A high time resolution and low-power ASIC for MRPC applications

The structure of readout circuits needs to be improved to meet the requirements of the endcap time of flight upgrade with multi-gap resistive plate chamber (MRPC) in Beijing Spectrometer III experiments, posing a demand for the high time resolution and low-power electronics. Considering MRPC features, an application-specific integrated circuit (ASIC) called FEEWAVE, which integrates the front-end circuit and digitization function, is proposed to meet the above requirements. The front-end circuit implements I/V conversion and signal amplification. To reduce power consumption and further improve the time resolution, the waveform sampling technique based on switch capacitor array is adopted. A 30 fC to 1.2 pC input signal dynamic range is obtained, and the jitter is less than 21 ps rms. At the same time, the chip realizes 5 GSPS (gigabit samples per second) sampling rate, trigger rate capability of 50 kHz and 25 mW/channel power consumption. The 6-channel ASIC has been designed and taped out with 0.18 $$\upmu $$m complementary metal oxide semiconductor technology. The preliminary test results of FEEWAVE have been achieved.

An LCC-Compensated Multiple-Frequency Wireless Motor System

In this paper, a novel kind of wireless motors, namely, the LCC -compensated wireless switched reluctance motor, is proposed and implemented. The definite advantages are that there is no power converter at the motor side and particularly no switched-capacitor array at the transmitter side to realize the multiple-frequency operation. The key is to develop an LCC compensation involving an inductor and two capacitors (the so-called LCC ) for a multiple-frequency wireless power transfer system. As a result, only one transmitter is needed to targetedly feed three receivers, which directly energize the three phase windings of the motor. Particularly, there is no need to control switched capacitors to change the resonant frequency of the transmitter. Meanwhile, the burst firing control method is employed to realize the speed control. Both calculation and experimental results are presented to validate the feasibility of the proposed system. In the system prototype, the transmission distance can reach up to 150 mm and the transmission efficiency can be achieved up to 80%.

A digitally tunable small-area composite-varactor array operated with positive and negative control voltages for high linearity and low loss RF circuit applications

A small-area composite-varactor-based digitally tunable capacitor operated with positive and negative control voltages is proposed to remove several drawbacks resulting from the metal–insulator-metal (MIM) capacitor of the conventional switched capacitor array (SCA). It was constructed with several composite-varactor branches in parallel, each of which consists of p-type (P+/Pwell) and n-type (N+/Nwell) accumulation-mode varactors in a cascode configuration. The optimum ratio of the channel width between p-type and n-type accumulation-mode varactors was investigated through the simulation in order to maximize a quality factor (Q-factor) of the tunable capacitor at the maximum capacitance (CMAX) state. The number of composite-varactor unit in each branch was designed to be binary-weighted, and the total capacitance can vary linearly by digitally turning on and off both varactors. It was firstly implemented in 65-nm bulk CMOS process, and showed comparable tuning range, Q-factor, and harmonic distortion performances while reducing the silicon area by half and eliminating the MIM capacitor in comparison with the conventional SCA. In the measurement, the proposed tunable capacitor showed a Q-factor of 60.3 at CMAX state and a tuning range of 2.8 at 2 GHz frequency band. In addition, it was perfectly capable of handling a high power signal up to 0 dBm with excellent second and third-order harmonic distortion of greater than 70 dBc at the minimum capacitance (CMIN) state and 77 dBc at CMAX state.

An Integrated Discrete-Time Delay-Compensating Technique for Large-Array Beamformers

This paper implements a wide aperture high-resolution true time delay for frequency-uniform beamforming gain in large-scale phased arrays. We propose a baseband discrete-time delay-compensating technique to augment the conventional phase-shift-based analog or hybrid beamformers. A generalized design methodology is first developed to compare delay-compensating analog or hybrid beamforming architecture with their digital counterpart for a given number of antenna elements, modulation bandwidth, ADC dynamic range, and delay resolution. This paper shows that delay-compensating analog or hybrid beamformers are more energy-efficient for high dynamic-range applications compared to true-time-delay digital beamformers. To demonstrate the feasibility of our proposed technique, a four-element analog delay-compensating baseband beamformer in 65-nm CMOS is prototyped. A time-interleaved switched-capacitor array implements the discrete-time delay-compensating beamformer with a wide delay range of 15-ns and 5-ps resolution. Measured power consumption is 47 mW with frequency-uniform array gain over 100-MHz modulated bandwidth, independent of angle of arrival. The proposed delay compensation scheme is scalable to accommodate the delay differences for large antenna arrays with higher range/resolution ENOB compared with prior art.

GERO: a general SCA-based readout ASIC for micro-pattern gas detectors with configurable storage depth and on-chip digitizer

The paper presents GEneral ReadOut (GERO), a general readout ASIC based on a switched capacitor array for micro-pattern gas detectors. It aims at providing general readout electronics for low-to-medium event-rate gas detectors with high sampling frequency, configurable storage depth, and data digitalization. The first prototype GERO chip integrates 16 channels and was fabricated using a 0.18-µm CMOS process. Each channel consists of a sampling array working in a ping-pong mode, a storage array with a 1024-cell depth, and 32 Wilkinson analog-to-digital converters. The detailed design and test results are presented in the paper.

A 0.7-mW LC Voltage-Controlled Oscillator Leveraging Switched Biasing Technique for Low Phase Noise

A 0.8-V low-phase-noise voltage-controlled oscillator (VCO) by using 0.18- ${\mu }\text{m}$ CMOS process was proposed for a 2-GHz sliding-IF receiver. A noise filtering technique is utilized to reduce the thermal noise. Moreover, a switched biasing technique with gate voltage controlling is introduced for further lowering the phase noise and power consumption. By using a 3-bit binary-weighted switched capacitor array, the proposed VCO can achieve wide frequency tuning range. The measured results show the phase noise at 1 MHz offset frequency from the carrier signal is −123 dBc/Hz. The frequency tuning range is from 1.28 to 1.53 GHz. The power consumption is lower than 0.7 mW. The figure of merit is −193 dB.

Design and offline processing of an ultrafast digitizer based on internal cascaded DRS4

In this paper, we present an ultrafast digitizer utilizing the DRS4 switched capacitor array application-specific integrated circuit to achieve an ultrafast sampling speed of at most 5 GS/s. We cascaded all eight channels (sub-channels) of a single DRS4 chip for increased storage depth. The digitizer contains four DRS4 chips, a quad-channel analog-to-digital converter, a controlling field-programmable gate array, a PXI interface, and an SFP+ connector. Consequently, each DRS4 channel has a depth of 8192 points and a vertical resolution of 14 bits. The readout sequences should be broken into several segments and then reordered to obtain the correct sequential data sets, and this offline procedure varies in different readout modes. This paper describes the design and implementation of the hardware; in particular, the respective processing procedures are described in detail. Furthermore, the offset error is calibrated and corrected to improve the precision of the captured waveform in both single-channel and high-resolution modes.

Front-end electronic readout system for the Belle II imaging Time-Of-Propagation detector

The Time-Of-Propagation detector is a Cherenkov particle identification detector based on quartz radiator bars for the Belle II experiment at the SuperKEKB electron-positron collider. The purpose of the detector is to identify the type of charged hadrons produced in electron-positron collisions, and requires a single photon timing resolution below 100 picoseconds. A novel front-end electronic system was designed, built, and integrated to acquire data from the 8192 microchannel plate photomultiplier tube channels in the detector. Waveform sampling of these analog signals is done by switched-capacitor array application-specific integrated circuits. The processes of triggering, digitization of windows of interest, readout, and data transfer to the Belle II data acquisition system are managed by Xilinx Zynq-7000 programmable system on a chip devices.

Development of the Front-End Electronics for PandaX-III Prototype TPC

The Particle And Astrophysical Xenon Experiment III (PandaX-III) is an experiment to search for the Neutrinoless Double Beta Decay (NLDBD) using 200 kg radio-pure high-pressure gaseous xenon TPC with Micromegas detectors at both ends and cathode in the middle. A small-scale TPC equipped with 7 Microbulk Micromegas detectors is developed as the prototype detector. 128 channels are readout following an X-Y design with strips of 3 mm pitch (64 channels each direction) from one Micromegas module. Highly integrated front-end electronics composed of 4 front-end cards with 1024 readout channels is designed to readout the charge of Micromegas anode signals, digitize the waveform after shaping and send compressed data to the DCM board. The cornerstone of the front-end electronics is a 64-channel application specific integrated circuit which is based on a switched capacitor array. The integral nonlinearity of the front-end electronics is less than 1% with 1 pC. The noise (RMS) of each readout channel is less than 0.9 fC with 1 microsecond peaking time and 1 pC range. Using the radioactive sources 56 Fe and 137 Cs, joint-tests of front-end electronics with the prototype TPC were carried out and the hit map of 7 Micromegas has been reconstructed.

Integrated polychromator and data acquisition system for the Thomson scattering diagnostic

New experiments with higher electron temperatures in the gas dynamic trap (GDT) magnetic mirror require a substantial upgrade of the Thomson scattering diagnostic. The paper presents the recently developed polychromator based on interference filters, which has the data acquisition and processing system onboard. The six spectral channels have wavelength pass bands distributed from 900 nm to 1057 nm to enable measurements of the electron temperature in the range from 20 eV to approximately 2 keV . The optimized design of the detection module with the avalanche photodiode and the signal amplifier yields the transmission factor of 4× 106 V/W in the bandwidth of 1 to 50 MHz in the high-speed detection channel. For a 1064 nm laser pulse of 10 ns duration, the amplifier noise equivalent is only 30 photons. Every detection module is also equipped with the low-speed (0 to 1 kHz) detection channel for separate measurements of background plasma radiation. This option also enables an easy calibration of the spectral response function using a continuous-wave light source like tungsten lamp. The high-speed acquisition channel utilizes the “time stretch” principle. It uses the 5.5 GSample/s analog memory arranged in the switched capacitor array to hold the signal trace of 200 ns duration, which is then processed by a relatively slow 14-bit digitizer. The acquisition and readout sequence can be cycled at the frequency of up to 40 kHz providing the necessary time resolution in experiments with multiple laser beam pulses. The polychromator onboard data processing electronics is controlled by the System on Chip solution with the procedures of data processing implemented in the Field Programmable Gate Array. Lab test results along with first plasma measurements are presented in the paper.

Data Acquisition System for Thomson Scattering Diagnostics on GDT

This paper describes a data acquisition system for Thomson scattering diagnostics on a gas-dynamic trap (GDT) (the Budker Institute of Nuclear Physics, Novosibirsk, Russia). It allows recording scattered laser radiation pulses of ~10-ns duration with 5-GSPS sampling rate and 14-bit amplitude resolution. The data acquisition system includes eight-channel high-speed recorders and photodetector modules. The photodetector modules are based on avalanche photodiodes and low-noise transimpedance amplifiers. The recording module design uses switched-capacitor array technology.