Switched Capacitor Array Research Articles

Non-ideal effects of MOS capacitor in a switched capacitor waveform recorder ASIC**Supported by National Natural Science Foundation of China (11375100), Strategic Pioneer Program on Space Sciences, Chinese Academy of Sciences (XDA04060606-06) and State Key Laboratory of Particle Detection and Electronics

SCAs (Switched Capacitor Arrays) have a wide range of uses, especially in high energy physics, nuclear science and astrophysics experiments. This paper presents a method of using a MOS capacitor as a sampling capacitor to gain larger capacitance with small capacitor area in SCA design. It studies the non-ideal effects of the MOS capacitor and comes up with ways to reduce these adverse effects. A prototype SCA ASIC which uses a MOS capacitor to store the samples has been designed and tested to verify this method. The SCA integrates 32 channels and each has 64 cells and a readout amplifier. The stored voltage is converted to a pair of differential currents (±4 mA max) and multiplexed to the output. All the functionalities have been verified. The power consumption is less than 2 mW/ch. The INL of all the cells in one channel are better than 0.39%. The equivalent input noise of the SCA has been tested to be 2.2 mV with 625 kHz full-scale sine wave as input, sampling at 40 MSPS (Mega-samples per Second) and reading out at 5 MHz. The effective resolution is 8.8 bits considering 1 V dynamic range. The maximum sampling rate reaches up to 50 MSPS and readout rate of 15 MHz to keep noise smaller than 2.5 mV. The test results validate the feasibility of the MOS capacitor.

Design of Gigahertz Tuning Range 5 GHz LC Digitally Controlled Oscillator in 0.18 μm CMOS

Abstract In this paper design and simulation of a 4.3 - 5.4 GHz LC digitally controlled oscillator (LC DCO) in IBM 7RF 0.18 μm CMOS technology are presented. Wide gigahertz tuning range is achieved by using two LC DCOs, sharing same structure. DCO is made of one NMOS negative impedance transistor pair and LC tank, which consists of high quality inductor and two switched capacitor arrays for coarse and fine frequency tuning. Coarse and fine tuning switched capacitor arrays are controlled using 6-bit and 3-bit binary words. To increase available frequency values, frequency divider is used. Structure of frequency divider is based on extended-true-single-phase-clock flip-flops. Divider is made of eight divide-by-2 cells connected in daisy chain, thus division values from 2 to 256 are available. Wide tuning range and high division values allows using such DCO with frequency divider in multi-standart transceivers. Whole device is supplied from a single 1.8 V voltage source. At highest frequency proposed device draws 90 mA current including all buffers. Phase noise is −116.4 dBc/Hz at 1 MHz offset from 5.44 GHz carrier. Designed dual DCO and frequency divider occupies about 0.4mm×0.5mm of chip space and whole chip, including pads, occupies 1.5mm × 1.5mm area of silicon.

146 - Construction and first tests of a PET-like detector for hadrontherapy beam ballistic control

We present the first results obtained with a detector, called Large Area Pixelized Detector (LAPD), dedicated to the beam ballistic control in the context of hadrontherapy. The purpose is to control the ballistics of the beam delivered to the patient by in-beam and real time detection of secondary particles, emitted during its irradiation. These particles could be high energy photons (γ prompt), or charged particles like protons, or 511 keV γ from the annihilation of a positron issued from the β+ emitters induced in the patient tissues along the beam path. These methods require being able to detect with a huge efficiency, and with a minimum dead time, these secondary particles emitted when the beam hits the patient. The LAPD is similar to a conventional Positron Emission Tomography camera. The 511 keV γ are detected and the reconstructed line of responses allow to measure the β+ activity distribution. Nevertheless, when trying to use γ from positron annihilations for the ballistic control in hadrontherapy, the large γ prompt background should be taken into account and properly rejected. This detector is made of two half-rings of 120 channels each. Each channel consists of a 13*13*15 mm3 LYSO crystal glued to a PMT. The PMT signal is sent to an Analog Sampling Module (ASM board). This VME 6U board is based on the DRS4 chip technology (Switch Capacitor Array) from the Paul Sherrer Institute and was specially designed for the LAPD detector. This board receives up to 24 differential analog input signals, with maximum amplitude of 600 mV, digitized by 12 bits - 33 MHz ADC. The sampling rate varies between 1 and 5 GHz, for a maximum buffer size of 1024 samples. The first part of the talk is devoted to the description of the detector and its electronics. Then, we describe the various trigger strategy, and the on-going upgrade of the VME-based acquisition system to a μTCA-based technology. The selection of the coincident 511 keV γ is also discussed, and the reconstruction using an iterative MLEM algorithm is presented. In the last part of the talk, few results from an experiment with one third of the detector, using proton and carbon ion beams at the Heidelberg Ion-Beam Therapy Center in 2014, are also described, and the Coincidence Resolution Time and energy resolution are given. First reconstruction results, obtained with a phantom filled with a high intensity FDG source at the cancer research center of Clermont- Ferrand in 2015 are also shown. This detector is now characterized, and will be installed at the Lacassagne hadrontherapy center (Nice, France), on the 65 MeV line (Medicyc) in December 2015 first, and on the future 230 MeV line (S2C2 from IBA) in 2016. The capability of this detector and its associated electronics to measure the ballistic of the proton beam in real clinical conditions with a sufficient precision will be evaluated.

Wide band low phase noise QVCO based on superharmonic injection locking**Project supporteded by the National Natural Science Foundation of China (No. 41274047) and the Guangdong Province Science and Technology Program (No. 2013B090500049).

A wide band, injection-coupled LC quadrature voltage control oscillator is presented. In the proposed circuit, two oscillators are injection locked by coupling their second-order harmonics in anti-phase, forcing the outputs of two oscillators into a quadrature phase state. As the common-mode point sampling the second harmonic frequency, flicker noise of the tail current is suppressed, the phase noise is reduced. The proposed design accomplishes a wide tuning frequency range by a combination of using a 5-bit switch capacitor array (SCA) for discrete tuning in addition to linearly varying AMOS varactors for continuous tuning. The proposed design has been fabricated and verified in a 0.18 μm TSMC CMOS technology process. The measurement indicates that the quadrature voltage controlled oscillator has a 41.7% tuning range from 3.53 to 5.39 GHz. The measured phase noise is 127.98 dBc/Hz at 1 MHz offset at a 1.8 V supply voltage with a power consumption of 12 mW at a carrier frequency of 4.85 GHz.

A class-C VCO based Σ–Δ fraction-N frequency synthesizer with AFC for 802.11ah applications

A 1.4–2 GHz phase-locked loop (PLL) Σ–Δ fraction-N frequency synthesizer with automatic frequency control (AFC) for 802.11ah applications is presented. A class-C voltage control oscillator (VCO) ranging from 1.4 to 2 GHz is integrated on-chip to save power for the sub-GHz band. A novel AFC algorithm is introduced to maintain the VCO oscillation at the start-up and automatically search for the appropriate control word of the switched-capacitor array to extend the PLL tuning range. A 20-bit third-order Σ–Δ modulator is utilized to reduce the fraction spurs while achieving a frequency resolution that is lower than 30 Hz. The measurement results show that the frequency synthesizer has achieved a phase noise of < −120 dBc/Hz at 1 MHz offset and consumes 11.1 mW from a 1.7 V supply. Moreover, compared with the traditional class-A counterparts, the phase noise in class-C mode has been improved by 5 dB under the same power consumption.

Conceptual design of the TRACE detector readout using a compact, dead time-less analog memory ASIC

The new TRacking Array for light Charged particle Ejectiles (TRACE) detector system requires monitorization and sampling of all pulses in a large number of channels with very strict space and power consumption restrictions for the front-end electronics and cabling. Its readout system is to be based on analog memory ASICs with 64 channels each that sample a 1μs window of the waveform of any valid pulses at 200MHz while discarding any other signals and are read out at 50MHz with external ADC digitization. For this purpose, a new, compact analog memory architecture is described that allows pulse capture with zero dead time in any channel while vastly reducing the total number of storage cells, particularly for large amounts of input channels. This is accomplished by partitioning the typical Switched Capacitor Array structure into two pipelined, asymmetric stages and introducing FIFO queue-like control circuitry for captured data, achieving total independence between the capture and readout operations.

Application of the DRS4 chip for GHz waveform digitizing circuits**Supported by National Natural Science Foundation of China (11305233), Specific Fund Research Based on Large-scale Science Instrument Facilities of China (2011YQ12009604)

A new fast waveform sampling digitizing circuit based on the domino ring sampler (DRS), a switched capacitor array (SCA) chip, is presented in this paper, which is different from the traditional waveform digitizing circuit constructed with an analog to digital converter (ADC) or time to digital converter. A DRS4 chip is used as a core device in our circuit, which has a fast sampling rate up to five gigabit samples per second (GSPS). Quite satisfactory results are acquired by the preliminary performance test for this circuit board. Eight channels can be provided by one board, which has a 1 V input dynamic range for each channel. The circuit linearity is better than 0.1%, the noise is less than 0.5 mV (root mean square, RMS), and its time resolution is about 50 ps. Several boards can be cascaded to construct a multi-board system. The advantages of high resolution, low cost, low power dissipation, high channel density and small size make the circuit board useful not only for physics experiments, but also for other applications.

A 0.1–6.0-GHz Dual-Path SDR Transmitter Supporting Intraband Carrier Aggregation in 65-nm CMOS

A 4.8-mm $^{2}~0.1$ –6.0-GHz dual-path software-defined radio transmitter supporting intraband carrier aggregation (CA) in 65-nm CMOS is presented. A simple approach is proposed to support intraband CA signals with only one I-Q baseband path. By utilizing the power-scalable and feedforward compensation techniques, the power of the wideband analog baseband is minimized. The transmitter consists of a high gain-range main path and a low-power subpath to cooperatively cover different standards over 0.1–6.0 GHz with more flexibility. The reconfigurable power amplifier (PA) driver achieves wideband frequency coverage with efficiency-enhanced on-chip transformers and improved switched-capacitor arrays. This transmitter achieves <−50-dBc image rejection ratio and <−40-dBc local oscillating signal leakage after the calibration. System verifications have demonstrated −31/−51-dBc ACLR1/ACLR2 (adjacent channel leakage ratio) at 3-dBm output power for 2.3-GHz LTE20 in the main path and 1.7% error vector magnitude (EVM) at 1.5-dBm output for 1.8-GHz WCDMA in the subpath. Both paths enable SAW-less FDD operations with −153 or −156 dBc/Hz carrier-to-noise ratio at 200-MHz frequency offset. Finally, the dual CA signals with 55-MHz frequency spacing are verified, showing the EVM of 1.2% and 0.8%, respectively, and exhibiting the intraband CA capability.

A mixed analog–digital fast hamming-weight filtering circuit using switched-capacitor arrays

Many circuit design applications rely on an intermediate sequence to carry a decision to the next circuit stage. The decision may be carried by a weighted pattern of N bits, with the weights being selected in a way that optimizes the circuit implementation or some aspect of performance. For example, when the weights are consecutive powers of 2 beginning with 1 = 20, we have the standard binary representation. As another example, when all the weights are 1, we have the unary representation that encodes a value k by k asserted bits and N---k unasserted bits (a weight-k bit vector of length N). In this paper, we present the design of a circuit that screens a unary representation to verify that the represented value falls between preset lower and upper limits l and u, passing through any string that represents a value in the interval [l, u] and outputting the all-0 s bit pattern otherwise. Our mixed analog---digital circuit implementation, based on switched-capacitor arrays, provides a decision output within a clock cycle of 4 ns for 16-bit unary representation, when realized with 0.15 μm TSMC technology. The latter results were obtained with normal, per-bit capacitance of 200 fF and single-clock-cycle operation. As an added benefit, our filtering circuit can form the basis for designing a cost-effective Hamming decoder circuit.

A 1 V 0.18 μm fully integrated integer-N frequency synthesizer for 2.4 GHz wireless sensor network applications

A 1 V low voltage, low power integer-N frequency synthesizer applied for 2.4 GHz wireless sensor network (WSN) applications is presented. The loop parameters of proposed charge pump phase lock loop frequency synthesizer is calculated and verified on the basis of continuous linear model. The proposed voltage controlled oscillator (VCO) consists of a PMOS cross-coupled transistor pair, a NMOS tail current source and a LC resonator. Common-mode 2nd harmonic filters are employed to improve loaded Q factor and suppress noise. LC resonator is optimized and switched capacitor array is used to lower AM---PM noise conversion. Fabricated in TSMC 0.18 μm CMOS process, the measured phase noise of VCO is ?113.4 dBc/Hz@1 MHz, and ?124.5 dBc/Hz@3.5 MHz while the frequency tuning range covers 4.56---5.32 GHz with 1 V voltage supply. The power dissipation is 2.3 mW and corresponding FOM is about ?185 dBc/Hz. With other blocks of dividers, phase frequency detector, charge pump and auto frequency calibration, the die area of the whole fabricated frequency synthesizer is 1.33 mm2 with pads. With 1 V supply voltage and 9.1 mW power consumption, the measured phase noise of the frequency synthesizer is ?121.9 dBc/Hz@1 MHz and ?134.4 dBc/Hz@3.5 MHz respectively, and the reference spur is ?44.5 dBc. The performance of the designed 1 V integer-N frequency synthesizer is suitable for IEEE 802.15.4/ZigBee based 2.4 GHz WSN applications.

Novel Calibration Method for Switched Capacitor Arrays Enables Time Measurements With Sub-Picosecond Resolution

Switched capacitor arrays (SCA) ASICs are becoming more and more popular for the readout of detector signals, since the sampling frequency of typically several gigasamples per second allows excellent pile-up rejection and time measurements. They suffer however from the fact that their sampling bins are not equidistant in time, given by limitations of the chip process. In the past, this limited time measurements of optimal signals to standard deviations ({\sigma}) of about 4-25 ps in accuracy for the split pulse test, depending on the specific chip. This paper introduces a novel time calibration, which determines the true sampling speed of an SCA. Additionally, for two independently running SCA chips, the achieved time resolution improved to less than 3 ps ({\sigma}) independently from the delay for the split pulse test, when simply applying a linear interpolation. When using a more advanced analyzing technique for the split pulse test with a single SCA, this limit is pushed below 1 ps ({\sigma}) for delays up to 8 ns. Various test measurements with different boards based on the DRS4 ASIC indicate that the new calibration is stable over time but not over larger temperature variations.

A self-calibration technique for wide tuning range PLLs

This paper presents a new calibration technique applicable for wide tuning range phase locked loops (PLLs) using very low gain voltage controlled oscillators (VCO). This technique uses the PLL main loop for the coarse and fine tuning of the VCO. Instead of using two loops which has been reported in previous works, in this work the VCO tuning voltage is used to calibrate the VCO switch capacitor array. Since the proposed calibration circuit operates in a closed loop form, it can be used for channel selection as well as adjusting for process, voltage and temperature variations. In addition, the calibration circuit has been used to set the VCO tail current in order to optimize VCO phase noise. A prototype frequency synthesizer has been designed in 0.18-μm CMOS process to work for a frequency range from 2.4 to 2.72 GHz. Simulation results show that using the proposed technique, a spur level of ?60 dB at 5 MHz offset from carrier was achieved while having negligible power overhead.

Design of a Low Phase Noise VCO for WSN Applications

A fully integrated LC VCO with 1V low voltage supply, applied in the frequency synthesizer for wireless sensor network applications, is designed and implemented in TSMC 0.18μm RF/MS CMOS process with low power consumption and good phase noise performance. To conquer the problems brought by low voltage, the structure of VCO is carefully selected. A 4 bit switched capacitor array is used to widen tuning range without worsen the phase noise performance. Besides, a 2 bit switched tail current source array is used to achieve power consumption adapted to the desired operating scenario. Second harmonic filter technology is taken to improve phase noise performance. The VCO designed in this paper has good phase noise performance and low power consumption by optimization. The chip size is 860μm×730μm. Post-simulation results show that the frequency range is between 4.57~6.18GHz with tuning range 30%, the center frequency is 5.375GHz, and the power consumption of VCO core is between 2.6~4mW. At the meanwhile, phase noise is between-116.0~ -117.8dBc@1.0MHz.

A 3.01–3.82 GHz CMOS LC voltage-controlled oscillator with 6.29% VCO-gain variation for WLAN applications

A wideband low-phase-noise LC voltage-controlled oscillator (VCO) with low VCO gain (KVCO) variation for WLAN fractional-N frequency synthesizer application is proposed and designed on a 0.13-μm CMOS process. In order to achieve a low KVCO variation, an extra switched varactor array was added to the LC tank with the conventional switched capacitor array. Based on the proposed switched varactor array compensation technique, the measured KVCO is 43 MHz/V with only 6.29% variation across the entire tuning range. The proposed VCO provides a tuning range of 23.7% from 3.01 to 3.82 GHz, while consuming 9 mA of quiescent current from a 2.3 V supply. The VCO shows a low phase noise of −121.94 dBc/Hz at 1 MHz offset, from the 3.6 GHz carrier.

Design of 4.48–5.89 GHz LC-VCO in 65 nm RF CMOS Technology

This paper describes a 4.48 GHz–5.89 GHz LC voltage-controlled oscillator (LC-VCO) as a key component in RF transceivers. The circuit is fully designed in TSMC’s 65 nm radio-frequency complimentary metal-oxide-semiconductor technology process. The LC-VCO uses the structure of only one couple of NMOS differential negative resistances, tank circuit which consists of an optimal on-chip spiral inductor with switched capacitor and varactor arrays. The proposed design accomplishes wide tuning range frequency by using 6-bit switch capacitor array in addition to linearly varying MOS varactors. A switched current source block is used to improve the performance of the LC-VCO. The oscillator has a wide tuning range, between 4.48 GHz and 5.89 GHz. The LC-VCO dissipates 15.96 mW from a voltage supply of 1.8 V, whereas its phase noise is -124.1 dBc/Hz at 1 MHz offset of a at 5.89 GHz carrier. DOI: http://dx.doi.org/10.5755/j01.eee.20.2.6383

Highly Linear Silicon-on-Insulator CMOS Digitally Programmable Capacitor Array for Tunable Antenna Matching Circuits

A stacked-FET linear 4-bit silicon-on-insulator (SOI) CMOS switched capacitor array is designed for use in tunable antenna matching circuits. A New biasing strategy without negative bias voltage is proposed to circumvent drawbacks such as digital switching noise and harmonics feed-through to the antenna. The proposed switched capacitor array shows almost identical power handling capability to that of the conventional version with negative bias voltage. Compared to other works in SOI or silicon-on-sapphire (SOS) technologies, it shows a comparable or better quality factor, tuning range, power handling capability, and harmonic distortion while consuming ultra low power.

A 15 GSa/s, 1.5 GHz bandwidth waveform digitizing ASIC

The PSEC4 custom integrated circuit was designed for the recording of fast waveforms for use in large-area time-of-flight detector systems. The ASIC has been fabricated using the IBM-8RF 0.13μm CMOS process. On each of the six analog channels, PSEC4 employs a switched capacitor array (SCA) of 256 samples deep, a ramp-compare ADC with 10.5 bits of DC dynamic range, and a serial data readout with the capability of region-of-interest windowing to reduce dead time. The sampling rate can be adjusted between 4 and 15Gigasamples/second (GSa/s) on all channels and is servo-controlled on-chip with a low-jitter delay-locked loop (DLL). The input signals are passively coupled on-chip with a −3dB analog bandwidth of 1.5GHz. The power consumption in quiescent sampling mode is less than 50mW/chip; at a sustained trigger and a readout rate of 50kHz the chip draws 100mW. After fixed-pattern pedestal subtraction, the uncorrected integral non-linearity is 0.15% over a 750mV dynamic range. With a linearity correction, a full 1V signal voltage range is available. The sampling timebase has a fixed-pattern non-linearity with an RMS of 13%, which can be corrected for precision waveform feature extraction and timing.

Techniques of Power Phase-Noise Optimization of 2.4 / 4.8 GHz CMOS VCO with Switched Capacitor Array Using Bondwire Inductor

This paper presents theoretical analysis of the maximum operating frequency of proposed Source Degeneration (SD) and Conventional CML D-Latch are estimated. The approach is based on the voltage transfer function, which is derived from small signal model of the circuit. Design approach with pre and post layout simulation results have been presented in detail and compared the performance in terms of power consumption, self oscillation frequency, sensitivity and supply voltage. With example shows the, all pMOS Voltage Controlled Oscilaator (VCO) with MOS capacitor switched capacitor array (SCA) generates the high frequency sinewave reference signals fed in to both divider for to get quadrature (Q) sinewave signals. Off Chip Bondwire inductor is used instead of on chip spiral inductor in all-pMOS VCO as it have high quality factor. Also, it will neglect the variations of carrier frequency and it gives additional performance like phase noise, power consumption, area than using spiral inductor. Even if use spiral inductor in all-pMOS VCO, Bondwire inductor also presents due to low impedance path between drain and ground terminal. Various optimization techniques are implemented while designing a QVCO, which facilitates is used to achieve a low power low phase noise performance. Compared to other types of QVCO, the conventional QVCO shows good phase noise performance than normally achieved 6 dB phase noise improvement with carrier frequency. The simulated results shows about 5 dB, 4 dB, 4 dB and 4 dB of phase noise improvement at 10 kHz, 100 kHz, 1 MHz and 3 MHz offset frequency from the 2.4 GHz carrier frequency. This combinational topology doesn't consume additional power and area than others and shows with improved phase noise performance. The pre and post layout simulation results are compared of both proposed (SD) and conventional QVCO, which is designed in 180 nm CMOS technology as 1V.

A dual-band quadrature VCO with gain proportional to oscillation frequency

This paper presents a novel dual-band quadrature voltage controlled oscillator (VCO) with the gain proportional to the oscillation frequency. Frequency synthesizers with this VCO can reduce the bandwidth fluctuation over all the frequency ranges without compensation or calibration. Besides the original switched capacitor array, an extra switched varactor array is adopted for the implementation of the proposed VCO. The tuning technique of changing the values of the capacitor and varactor at the same ratio is also derived. For verification purposes, a 2.5 G/3.5 G dual-band quadrature VCO is fabricated in a 0.13 μm CMOS process for WiMAX applications. Measurement results show that the VCO gain is closely proportional to the oscillation frequency with ±16% variation over the entire frequency range. The phase noise is −138.15 dBc/Hz at 10 MHz from the 2.5 GHz carrier and −137.44 dBc/Hz at 10 MHz from the 3.5 GHz carrier.

A Wideband 9 GHz LC-VCO with Tail Current Source Array in 0.18-μm RF CMOS Process

A wideband 9 GHz LC-VCO with tail current source array based on TSMC 0.18-μm RF CMOS process is presented in this paper. After discussing the start-up conditions, the structure of tail current source array is utilized to lower the power consumption in high frequency bands and guarantee start-up at low frequency bands. Furthermore, to extend the frequency range, a 4-bit switched capacitor array is used. Based on our analysis, a NMOS cross-coupled VCO with 4-bit PMOS tail current source array is implemented. Post-simulation results show that the tuning range is from 6.372GHz to 9.154GHz and the phase noise at 1MHz offset is less than-110dBc/Hz in the entire tuning range. The operating current of the VCO core is from 8.24mA to 13.362mA in the entire tuning range under 1.8V supply voltage. And the area of the proposed VCO is 1177.775μm × 577.54μm, with two buffer stages and pads.