Suppression Of Short-channel Effects Research Articles

Novel Gate-All-Around Poly-Si TFTs With Multiple Nanowire Channels

The novel gate-all-around (GAA) poly-Si thin-film transistors (TFTs) with multiple nanowire channels (MNCs) have been, for the first time, fabricated using a simple process to demonstrate high-performance electrical characteristics and high immunity to short-channel effects (SCEs). The nanowire channel with high body-thickness-to-width ratio (TFin/WFin), which is approximately equal to one, was realized only with a sidewall-spacer formation. Moreover, the unique suspending MNCs were also achieved to build the GAA structure. The resultant GAA-MNC TFTs showed outstanding three-dimensional (3-D) gate controllability and excellent electrical characteristics, which revealed a high on/off current ratio ( > 108), a low threshold voltage, a steep subthreshold swing, a near-free drain-induced barrier lowering, as well as an excellent SCE suppression. Therefore, such high-performance GAA-MNC TFTs are very suitable for applications in system-on-panel and 3-D circuits.

Self-aligned vertical double-gate MOSFET (VDGM) with the oblique rotating ion implantation (ORI) method

A process of making a symmetrical self-aligned n-type vertical double-gate MOSFET (n-VDGM) over a silicon pillar is revealed. This process utilizes the technique of oblique rotating ion implantation (ORI). The self-aligned region forms a sharp vertical channel profile and decreases the channel length Lg. A tremendous improvement in the drive-on current is noted. The electron concentration profile obtained demonstrates an increased number of electrons in the channel injected from the source end as the drain voltage increases. The enhanced carrier concentration results in significant reduction in the off-state leakage current and improves the drain-induced barrier-lowering (DIBL) effect. These simulated characteristics when compared to those in a fabricated device without the ORI method show the distinct advantage of the technique reported for suppression of short-channel effects (SCE) in nanoscale vertical MOSFET.

Short channel effect improved strained-Si:C-source/drain PMOSFETs

The suppression of short channel effect in strained-Si surface channel PMOSFET with carbon incorporation on relaxed SiGe buffers is demonstrated. The lateral diffusion of boron from source/drain into the channels is retarded by a reduction of interstitial formation due to carbon incorporation in the strained-Si layer. It is necessary to avoid the high temperature (>900 °C) process for SiC precipitations as trap centers which are observed by atomic force microscope and X-ray diffraction. An incorporated carbon in the source/drain is not only being stressor but also improves short channel effect for extremely shallow junctions, and makes it possible to have high speed devices.

The Potential of FinFETs for Analog and RF Circuit Applications

CMOS downscaling in the nanoscale era will necessitate drastic changes to the planar bulk CMOS transistor to keep pace with the required speed increase while at the same time maintaining acceptable performance in terms of leakage, variability and analog parameters such as gain, noise and linearity. For the gate electrode and the gate dielectric, which classically use polysilicon and with some amount of nitridation, new materials might be needed. Also, a new transistor architecture might be required that deviates from the planar structure. Thanks to their inherent suppression of short-channel effects, reduced drain-induced barrier lowering and good scalability, multi-gate devices such as fin-shaped field-effect transistors (FinFETs) are considered as possible candidates for device scaling at the end of International Technology Roadmap for Semiconductors. As such, they form a first step between a planar architecture and a silicon nanowire. In this paper, we demonstrate with functional prototypes of analog and RF circuits that the combination of a new gate stack with a FinFET transistor architecture outperforms comparable circuit realizations in planar bulk CMOS for low to moderate speed. Further, the FinFETs exhibit less leakage and show less intra-die variability than their planar bulk counterpart. In the microwave and millimeter-wave frequency region, planar bulk CMOS is still superior. The main challenge for FinFET performance in the coming years is the improvement of the maximum cutoff frequency, which is nowadays limited to 100 GHz.

Suppression of short channel effect in organic thin film transistors

Short-channel effect in organic thin film transistors with top-contact configuration is effectively suppressed to enhance the performance. The space charge limited current, which prevents the appearance of output saturation behavior, is sufficiently suppressed by reducing the thickness of both the pentacene film and the gate insulator. Molecular doping of the pentacene thin film in the contact reduces the contact resistance and allows a greater increase in field-effect mobility with decreasing channel length. These structural optimizations realize a submicrometer-channel transistor with clear saturation characteristics and low-voltage operation.

GaN-based FETs using Cat-CVD SiN passivation for millimeter-wave applications

We have found that SiN passivation by catalytic chemical vapor deposition (Cat-CVD) can significantly increase an electron density of an AlGaN/GaN heterostructure field-effect transistor (HFET). This effect enables thin-barrier HFET structures to have a high-density two-dimensional electron gas and leads to suppression of short-channel effects. We fabricated 30-nm-gate Al 0.4Ga 0.6N(8 nm)/GaN HFETs using Cat-CVD SiN. The maximum drain current density and extrinsic transconductance were 1.49 A/mm and 402 mS/mm, respectively. Current-gain cutoff frequency and maximum oscillation frequency of the HFETs were 181 and 186 GHz, respectively. These high-frequency device characteristics are sufficiently high enough for millimeter-wave applications.

Novel Gate-All-Around Metal–Oxide–Semiconductor Field Effect Transistors with Self-Aligned Structure

We proposed a new self-aligned gate-all-around metal–oxide–semiconductor field effect transistor (MOSFET) with a wide source/drain region. The device was fabricated by using the concept of the self-aligned double-gate fin-type FETs (FinFETs) with additional processes. The minimum gate length and fin width were 35 and 20 nm, respectively. The gate oxide thickness was 2.4 nm. For the fabricated devices, we confirmed that drain induce barrier lowering (DIBL) and sub-threshold swing (SS) were properly suppressed in spite of the short channel length. We also performed a simulation-based analysis to explore the effects induced by oversized bottom gate in the proposed device structure. If the lateral source/drain doping gradient was not steep, the oversized bottom gate could lead to the enhancement of the gate controllability and the suppression of short channel effects. As a result, the intrinsic gate delay of the proposed devices was improved when the bottom gate was somewhat oversized.

Device Design of Nanoscale MOSFETs Considering the Suppression of Short Channel Effects and Characteristics Variations

The device design of future nanoscale MOSFETs is reviewed. Major challenges in the design of the nanometer MOSFETs and the possible solutions are discussed. In this paper, special emphasis is placed on the combination of new transistor structures that suppress the short channel effect and on back-gate voltage control that suppresses the characteristics variations. Two new device architectures, variable-body-factor FD SOI MOSFET and multigate MOSFET with low aspect ratio, have been proposed and their advantages are discussed.

Characterization and simulation studies on high tilt ion implantation for precision halo implant applications

Precision dopant placement at high tilt angles for halo applications is required in the fabrication of advanced devices to achieve better transistor characteristics, such as suppression of short channel effects, Vt control and drive current. However, monitoring high tilt implants is not popular in semiconductor fabs, even though most have started monitoring zero-tilt implants in the recent couple of years. In this paper, the authors explore the possibilities of using high tilt angles with higher Miller Index channels. As an example, axial channeling along the 〈112〉 direction is used to evaluate the angle control performance of the VIISta 810EHP medium current ion implanter. Crystal-TRIM (a Monte Carlo simulation code) calculations are compared with experimental SIMS (Secondary Ion Mass Spectrometry) profiles. In addition, the effects of wafer orientation on the platen and wafer mis-cut on the dopant profiles are discussed. Metrology characterization, such as ThermaWaveTM and SIMS, of the 〈112〉 ion channeling is presented.

Impact of graded channel (GC) design in fully depleted cylindrical/surrounding gate MOSFET (FD CGT/SGT) for improved short channel immunity and hot carrier reliability

In the present paper, a two-dimensional (2-D) analytical model for graded channel fully depleted cylindrical/surrounding gate MOSFET (GC FD CGT/SGT) has been developed by solving the Poisson’s equation in cylindrical coordinates. An abrupt transition of silicon film doping at the interface has been assumed and the effects of the doping and the lengths of the high and low doped regions have been taken into account. The model is used to obtain the expressions of surface potential and electric field in the two regions. The analysis is extended to obtain the expressions for threshold voltage ( V th) and subthreshold swing. It is shown that a graded doping profile in the channel leads to suppression of short channel effects (SCEs) like threshold voltage roll-off, drain induced barrier lowering (DIBL) and hot carrier effects. The results so obtained have been compared with simulated results obtained using the device simulator ATLAS 3D and are found to be in good agreement.

Performance Investigation of 50-nm Insulated-Shallow-Extension Gate-Stack (ISEGaS) MOSFET for Mixed Mode Applications

An extended study of electrical characteristics of 50-nm single-material-gate insulated-shallow-extension-gate-stack (ISEGaS) MOSFET is performed using ATLAS-2D. Incorporation of dual-material-gate architecture leads to the suppression of short channel effects along with the improvement in device intrinsic gain (gmtimesRout), voltage gain (gm/IDS), and Ion/Ioff ratio, thereby opening a new era of ISEGaS MOSFETs for mixed mode applications

Design and simulation of a nanoelectronic DG MOSFET current source using artificial neural networks

The double gate (DG) MOSFET has received great attention in recent years owing to the inherent suppression of short channel effects (SCEs), excellent subthreshold slope (S), improved drive current (Ids) and transconductance (gm), volume inversion for symmetric devices and excellent scalability. Therefore, simulation tools which can be applied to design nanoscale transistors in the future require new theory and modeling techniques that capture the physics of quantum transport accurately and efficiently. In this sense, this work presents the applicability of the artificial neural networks (ANN) for the design and simulation of a nanoelectronic DG MOSFET current source. The latter is based on the 2D numerical Non-Equilibrium Green's Function (NEGF) simulation of the current–voltage characteristics of an undoped symmetric DG MOSFET. Our results are discussed in order to obtain some new and useful information about the ULSI technology.

Optimization of the source/drain extension region profile for suppression of short channel effects in sub-50 nm DG MOSFETs with high-κ gate dielectrics

In the present paper, we propose a new scaling theory to model short channel effects (SCEs) in nanoscale double gate (DG) SOI MOSFETs, addressing two important technological issues—source/drain extension (SDE) region engineering and high-κ gate dielectrics. The impact of SDE region engineering through the optimization of lateral source/drain doping gradient and spacer width on SCEs is extensively analysed in DG devices with high-κ gate dielectrics, using the analytical model and 2D device simulations. Novel technology dependent scaling parameters, i.e., spacer-to-gradient ratio (ρ) and effective channel length (Leff), are proposed for source/drain-engineered DG MOSFETs, and their significance in minimizing SCEs in high-κ gate dielectrics is discussed in detail. Results show that the optimal spacer-to-gradient ratio should be increased with the permittivity of high-κ dielectrics in order to maintain SCEs to an acceptable level. The results of the analytical model confirm well with simulated data over the entire range of spacer widths, doping gradients, high-κ gate dielectrics and effective channel lengths. The present work provides valuable design insights in the performance of nanoscale source/drain-engineered DG SOI devices with high-κ gate dielectrics and serves as an accurate tool to optimize important device parameters aiding technology development.

Suppression of short-channel effects in organic thin-film transistors

To improve the speed of organic thin-film transistor (TFT) circuits device architectures with submicrometer channel length are of interest. However, in conventional, submicrometer TFT structures the performance is degraded as a result of short-channel effects. Here we present an architecture for short-channel organic TFTs which is based on incorporating an insulating mesa structure in between source and drain electrodes. For submicrometer organic TFTs the mesa structure results in a significant enhancement of the on-off ratio and saturation characteristics. Device modeling shows that the mesa improves the ability of the gate electrode to modulate the carrier concentration in a submicrometer channel.

STUDY OF DUAL-MATERIAL GATE (DMG) FinFET USING THREE-DIMENSIONAL NUMERICAL SIMULATION

In this work, the novel characteristics of a FinFET with dual-material gate (DMG) are explored theoretically using a 3D numerical simulator and compared with those of a single material gate (SMG) FinFET in terms of threshold voltage roll off, drain induced barrier lowering (DIBL) and the ratio of transconductance (gm) to drain conductance (gd). Our studies show that the DMG structure achieves simultaneous suppression of short channel effects (SCEs), enhancement in carrier transport efficiency and transconductance. Also, these features can be controlled by engineering the work function and length of gate material.

An assessment of single-electron effects in multiple-gate SOI MOSFETs with 1.6-nm gate oxide near room temperature

This letter provides an assessment of single-electron effects in ultrashort multiple-gate silicon-on-insulator (SOI) MOSFETs with 1.6-nm gate oxide. Coulomb blockade oscillations have been observed at room temperature for gate bias as low as 0.2 V. The charging energy, which is about 17 meV for devices with 30-nm gate length, may be modulated by the gate geometry. The multiple-gate SOI MOSFET, with its main advantage in the suppression of short-channel effects for CMOS scaling, presents a very promising scheme to build room-temperature single-electron transistors with standard silicon nanoelectronics process.

Punch-through in short-channel AlGaN/GaN HFETs

Short-channel punch-through effects are demonstrated in 0.17 /spl mu/m gate length AlGaN/GaN single heterojunction field-effect transistors. These take the form of a high output conductance and the strong dependence of pinch-off voltage on drain voltage. It is shown by simulation that they can be explained by poor confinement of charge at the AlGaN/GaN interface resulting in current flow within the bulk of the GaN layer. This is caused by there being a concentration of only /spl sim/1.5/spl times/10/sup 16/ cm/sup -3/ deep levels in the insulating GaN buffer layer. It is found that a net acceptor density of around 10/sup 17/ cm/sup -3/ is required to ensure suppression of short-channel effects.

High Performance pMOSFETs with High Ge Fraction Strained SiGe-heterostructure-channel and Ultrashallow Source/Drain Formed by Selective B-Doped SiGe CVD

The improvement of current drivability and short channel effect is very important for ultrasmall MOS devices technology. SiGe-channel pMOSFETs are one of the most promising devices because hole mobility in the SiGe layers is enhanced. In the previous work, it has been reported that Super self-aligned shallow junction electrode (S3E) MOSFETs formed by selective B-doped SiGe CVD are effective for the suppression of short channel effect. In this paper, it is clarified that the (S3E) pMOSFETs with Si0.65Ge0.35-channel are realized not only with suppression of punch through due to the ultrashallow B-diffused source/drain but also with enhancement of maximum linear transconductance due to the low parasitic resistance, compared to that with the Si-channel fabricated by the same process conditions.

A Comparative Study of Electrical Characteristic on Sub-10-nm Double-Gate MOSFETs

We explore the structure effect on electrical characteristics of sub-10-nm double-gate metal–oxide–semiconductor field-effect transistors (DG MOSFETs). To quantitatively assess the nanoscale DG MOSFETs' characteristics, the on/off current ratio, subthreshold swing, threshold voltage <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$( V_ th)$</tex> , and drain-induced barrier-height lowering are numerically calculated for the device with different channel length ( <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$L$</tex> ) and the thickness of silicon film <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$( T_ si)$</tex> . Based on our two-dimensional density gradient simulation, it is found that, to maintain optimal device characteristics and suppress short channel effects (SCEs) for nanoscale DG MOSFETs, <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$ T_ si$</tex> should be simultaneously scaled down with respect to <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$L$</tex> . From a practical fabrication point-of-view, a DG MOSFET with ultrathin <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$ T_ si$</tex> will suppress the SCE, but suffers the fabrication process and on-state current issues. Simulation results suggest that <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$ L/ T_ si geq 1$</tex> may provide a good alternative in eliminating SCEs of double-gate-based nanodevices.

Control of Threshold-Voltage and Short-Channel Effects in Ultrathin Strained-SOI CMOS Devices

This paper presents a quantitative study on the device design for the control of threshold-voltage and the suppression of short-channel effects (SCEs) in ultrathin strained-silicon-on-insulator (strained-SOI) CMOSFETs in the sub-100-nm regime. A two-dimensional device simulation is used for this purpose, with emphasis on the impact of band offset in Si/SiGe heterostructures. For the control of threshold-voltage, the combination of the gate work function and the back gate bias is needed to obtain appropriate values of threshold-voltage in n- and p-channel MOSFETs and to suppress SiGe buried channels in p-channel MOSFETs with thicker strained-Si layers. Regarding SCEs, the importance and the necessity of thin SiGe layers are pointed out from the viewpoint of the influence of the higher permittivity of SiGe layers. It is shown that the SCEs of strained-SOI MOSFETs with thinner SiGe layers are almost the same level as those of unstrained-SOI.