Suppression Of Short-channel Effects Research Articles

Investigation of the Novel Attributes of a Fully Depleted Dual-Material Gate SOI MOSFET

The novel features of a fully depleted (FD) dual-material gate (DMG) silicon-on-insulator (SOI) MOSFET are explored theoretically and compared with those of a compatible SOI MOSFET. The two-dimensional numerical simulation studies demonstrate the novel features as threshold voltage roll-up and simultaneous transconductance enhancement and suppression of short-channel effects offered by the FD DMG SOI MOSFET. Moreover, these unique features can be controlled by engineering the workfunction and length of the gate material. This work illustrates the benefits of high-performance FD DMG SOI MOS devices over their single material gate counterparts and provides an incentive for further experimental exploration.

Suppression of short-channel effect in pseudomorphic In0.25Al0.75P/In0.75Ga0.25As high electron mobility transistors

Pseudomorphic In0.25Al0.75P/In0.75Ga0.25As high electron mobility transistors (HEMTs) were fabricated to investigate the short-channel effect in the sub-0.1-µm gate-length region. Employing a thin Schottky barrier and a thin channel layer structure enabled us to suppress the short-channel effect in short-gate HEMTs, and a high-performance 47-nm-gate HEMT with a 423-GHz current gain cutoff frequency was achieved. The present results show the possibility of the practical use of pseudomorphic HEMTs with a scaled-down structure for various applications, such as ultra-high-speed digital circuits and millimeter-wave communications/observations.

Design of 50-nm Vertical MOSFET Incorporating a Dielectric Pocket

A new architecture for a vertical MOS transistor is proposed that incorporates a so-called dielectric pocket (DP) for suppression of short-channel effects and bulk punch-through. We outline the advantages that the DP brings and propose a basic fabrication process to realize the device. The design issues of a 50-nm channel device are addressed by numerical simulation. The gate delay of an associated CMOS inverter is assessed in the context of the International Technology Roadmap for Semiconductors and the vertical transistor is seen to offer considerable advantages down to the 100-nm node and beyond due to the dual channels and the ability to produce a 50-nm channel length with more relaxed lithography.

Subthreshold behavior of triple-gate MOSFETs on SOI material

The fabrication of n-type multi-wire MOSFETs on SOI material with triple-gate structures is presented. The output and transfer characteristics of devices with a gate length of 70 nm and a MESA width of 22 nm demonstrate clearly the suppression of short channel effects (SCE). In addition, these triple-gate structures are compared with planar SOI devices of comparable dimensions. The influence of biasing the substrate (back gate) is analyzed and compared to simulation data.

Fabrication of 0.12 μm pMOSFETs on high Ge fraction Si/Si 1− xGe x/Si(1 0 0) heterostructure with ultrashallow source/drain formed using B-doped SiGe CVD

High Ge fraction Si/Si 1− x Ge x /Si heterostructures ( x=0.5) are processed into the super self-aligned ultrashallow junction electrode (S 3E) pMOSFETs. The ultrashallow junction is made from the selective epitaxial B-doped Si 0.5Ge 0.5 on source/drain grown by chemical vapor deposition (CVD) and subsequent thermal diffusion of B from B-Si 0.5Ge 0.5 into the substrate. The Ge fraction in the S 3EMOSFETs’ buried layer changes to 0.35 after the B diffusion at 750 °C due to the interdiffusion between Si and Ge. The B diffusion depth in Si/SiGe/Si is shallower compared to that in Si. Compared to Si-channel S 3EMOSFET, the maximum linear transconductance of the 0.12 μm gate Si 0.65Ge 0.35-channel S 3EMOSFET increases by approximately 45%. The threshold voltage shift and the S factor degradation in the short channel region are well suppressed compared to the Si-channel S 3EMOSFETs. It is suggested that the suppression of short channel effects is caused by the ultrashallow source/drain and the valence band discontinuity at the Si 1− x Ge x /buffer Si interface.

A comprehensive study of indium implantation-induced damage in deep submicrometer nMOSFET: device characterization and damage assessment

The impact of indium channel implantation on the current-voltage characteristics, gate oxide breakdown and hot-carrier reliability of deep submicrometer nMOSFETs is studied in detail. A significantly faster oxide wear-out during ramped-voltage testing and a distinctly enhanced drain current degradation during hot-carrier stressing are observed in devices with implant dose ranging from 1-2 /spl times/ 10/sup 13/ cm/sup -2/. An important generation leakage is also measured in the long-channel MOSFET, although such irregularity is normally not detected in short-channel devices owing to predominant subthreshold current. The loss in device reliability may be attributed to the generation of local amorphous regions in the channel when the implant dose exceeds 10/sup 13/ cm/sup -2/. The limited thermal budget of the subsequent gate oxidation step is generally unable to anneal out these defects, which in turn lead to the formation of local weak spots and strained Si-H bonds in the gate oxide, and dislocation loops in the channel region. This finding raises an important concern on the use of indium implantation in retrograde channel engineering, since implant doses on the order of 10/sup 13/ cm/sup -2/ are often needed for effective suppression of short-channel effects. In order to minimize the loss in device reliability, the damaged lattice would need to be restored using a dedicated thermal annealing cycle prior to gate oxidation. A good correlation between the hot-carrier stress data and the DC current-voltage (DCIV) measurement data is also presented. This makes the DCIV technique a precise, nondestructive monitor for implantation-induced damage in deep submicrometer MOSFET, via a direct measurement of the process-residue interface traps.

Damascene W/TiN gate MOSFETs with improved performance for 0.1-μm regime

W/TiN gate CMOS technologies with improved performance were investigated using a damascene metal gate process. 0.1-/spl mu/m W/TiN stacked gate CMOS devices with high performance and good driving ability were fabricated successfully by optimizing the W/TiN stacked gate structure, improving the W/TiN gate electrode sputtering technology, and reducing W/TiN stacked gate MOSFET surface states and threshold voltages. A super steep retrograde (SSR) channel doping with heavy ion implantation, /sup 115/In/sup +/ for NMOS and /sup 121/Sb/sup +/ for PMOS, was applied here to obtain a reasonably lower threshold voltage and to suppress short-channel effects (SCEs). Non-CMP technology, used to replace CMP during the damascene metal gate process, was also explored. The propagation delay time of 57 stage W/TiN gate CMOS ring oscillators was 13 ps/stage at 3 V and 25 ps/stage at 1.5 V, respectively. Better performance would be achieved by using Co/Ti salicide source/drain (S/D) and thinner gate dielectrics.

Sub-40 nm SOI V-groove n-MOSFETs

We present output and transfer characteristics of single-gated, 36 nm, 46 nm and 56 nm channel length SOI MOSFETs with a V-groove design. For the shortest devices we find transconductances as high as 900 μS/μm and drive currents of 490 μA/μm at V/sub gs/ - V/sub th/=0.6 V. The V-groove approach combines the advantages of a controlled, extremely abrupt doping profile between the highly doped source/drain and the undoped channel region with an excellent suppression of short-channel effects. In addition, our V-groove design has the potential of synthesizing devices in the 10 nm range.

Design and fabrication of 50-nm thin-body p-MOSFETs with a SiGe heterostructure channel

Thin-body p-channel MOS transistors with a SiGe/Si heterostructure channel were fabricated on silicon-on-insulator (SOI) substrates. A novel lateral solid-phase epitaxy process was employed to form the thin-body for the suppression of short-channel effects. A selective silicon implant that breaks up the interfacial oxide was shown to facilitate unilateral crystallization to form a single crystalline channel. Negligible threshold voltage roll-off was observed down to a gate length of 50 nm. The incorporation of Si/sub 0.7/Ge/sub 0.3/ in the channel resulted in a 70% enhancement in the drive current. This is the smallest SiGe heterostructure-channel MOS transistor reported to date. This is also the first demonstration of a thin-body MOS transistor incorporating a SiGe heterostructure channel.

Suppression of short channel effects by full inversion in deep sub-micron gate SOI MOSFETs

Classical modeling of fully inverted SOI MOSFET (FI MOSFET) has been performed. In FI MOSFETs, the top Si layer is thinner than the thickness of the inversion layer at the conducting state and so the depleted region in the top Si layer is completely eliminated. It was found that the gate electric field induces carriers in the channel more effectively in FI MOSFET than in the fully depleted SOI MOSFETs (FD MOSFET), so that the short channel effects can be suppressed significantly.

A Partial-Ground-Plane (PGP) Silicon-on-Insulator (SOI) Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) for Deep Sub-0.1-µm Channel Regime

Silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistor (MOSFET) offers a number of advantages over conventional bulk silicon transistors. In this paper, we present a new SOI device structure called a “partial-ground-plane” SOI MOSFET down to 50 nm channel length. This new device shows good suppression of short-channel effect together with a small subthreshold swing and has a good driveability with a low leakage current.

Dielectric pockets-a new concept of the junctions for deca-nanometric CMOS devices

A new concept of dielectric pockets is proposed allowing suppression of short-channel effects (SCEs) and DIBL without increasing the channel doping. The dielectric pockets have been implanted into 0.15-/spl mu/m PMOS devices showing substantial efficiency in reducing SCE and I/sub OFF/ current without altering the current drive. The dielectric pockets thus embody the ideal pocket architecture.

Exploring the novel characteristics of hetero-material gate field-effect transistors (HMGFETs) with gate-material engineering

The novel characteristics of a new type of MOSFET, the hetero-material gate field-effect transistor (HMGFET), are explored theoretically and compared with those of the compatible MOSFET. Two conceptual processes for realizing the HMG structure are proposed for integration into the existing silicon technology. The two-dimensional (2-D) numerical simulations reveal that the HMGFET demonstrates extended threshold voltage roll-off to much smaller length and shows simultaneous transconductance enhancement and suppression of short-channel effects (SCEs) [drain-induced barrier-lowering (DIBL) and channel-length modulation (CLM)] and, more importantly, these unique features could be controlled by engineering the material and length of the gate. This work demonstrates a new way of engineering ultrasmall transistors and provides the incentive and guide for experimental exploration.

A high performance 0.15 μm buried channel pMOSFET with extremely shallow counter doped channel region using solid phase diffusion

A new process for a counter-doped region suitable for a 0.15 μm (gate length) buried channel (BC) pMOSFET is presented. At present serious short-channel effects of BC p-MOSFETs are recognized broadly as prohibitive for application at 0.1 μm. In order to realize 0.15 μm BC pMOSFETs, we propose a new process step, making use of a boron solid phase diffused channel (SPDC) from a Boron-doped silicate glass (BSG) to form an extremely shallow counter-doped region, which enables suppression of short-channel effects. Devices fabricated in this way exhibit good short-channel behavior at 0.15 μm gate length and, additionally, provide an excellent current driving-ability. Threshold voltage control is easy by optimizing the diffusion condition. We propose SPDC as a suitable process applicable to 0.2–0.1 μm BC p-MOSFET.

Decaborane (B/sub 10/H/sub 14/) ion implantation technology for sub-0.1-μm PMOSFET's

A low-energy, high-dosage boron ion implantation technology using a decaborane (B/sub 10/H/sub 14/) molecule is developed. Since B/sub 10/N/sub 14/ consists of ten boron atoms, they are implanted with about a one-tenth lower effective acceleration energy and ten times higher effective beam current compared with those of boron. We demonstrated an ultrashallow boron profile with 0.5 keV effective acceleration energy, which does not cause transient enhanced diffusion (TED) after rapid thermal annealing (RTA). Using this technology, we succeeded in fabricating 0.1-/spl mu/m PMOSFET's with good device performances and excellent suppression of short-channel effects.

Single electron tunneling and suppression of short-channel effects in submicron silicon transistors

We report measurements on submicron metal–oxide–semiconductor field effect transistors equipped with a gate on three sides of the channel. At room temperature, a strong suppression of short-channel effects has been achieved for the narrowest channels. At liquid helium temperatures, the same devices exhibit clear conductance oscillations in the subthreshold regime, indicating that a quantum dot has formed in the disordered channel.

Short Channel Effects in N- and P-Channel Polycrystalline Silicon Thin Film Transistors with Very Thin Electron Cyclotron Resonance N2O-Plasma Gate Dielectric

To suppress short-channel effects in polysilicon thin film transistors, very thin electron cyclotron resonance (ECR) N2O-plasma gate oxide is investigated experimentally. ECR N2O-plasma oxidation incorporates nitrogen atoms at the interface and forms strong Si≡N bonds. With the ECR N2O-plasma oxide of 12 nm thickness, short-channel effects can be almost eliminated for n-channel (p-channel) thin film transistors of 3 µm (1 µm) gate length. It is inferred that reduction of defects by N2O-plasma passivation and strong Si≡N bonds lead to good immunity to impact ionization, resulting in the suppression of short-channel effects.

Monte Carlo study of 50 nm-long single and dual-gate MODFETs: suppression of short-channel effects

A theoretical study of 50 nm-Single and Dual-Gate MODFETs using Monte Carlo simulation is reported. The introduction of a second gate, whose potential is fixed to a positive value, between the control-gate and the drain allows to efficiently provide against short-channel effects that occur in ultra-short single-gate MODFET. We describe the physical operating of these devices and especially the role of the second gate. The dual-gate MODFET exhibits an excellent saturation behaviour compared with single-gate MODFETs together with high values of transconductance g m and current gain cutoff frequency f T . This is resulting in a large improvement in the g m to g D ratio

Silicon-hydrogen bonds and microvoids in hydrogenated amorphous silicon and Staebler-Wronski effect: G. G. Qin and G. L. Kong. Solid-St. Commun.71(1), 41 (1989)

A new process for a counter-doped region suitable for a 0.15 μm (gate length) buried channel (BC) pMOSFET is presented. At present serious short-channel effects of BC p-MOSFETs are recognized broadly as prohibitive for application at 0.1 μm. In order to realize 0.15 μm BC pMOSFETs, we propose a new process step, making use of a boron solid phase diffused channel (SPDC) from a Boron-doped silicate glass (BSG) to form an extremely shallow counter-doped region, which enables suppression of short-channel effects. Devices fabricated in this way exhibit good short-channel behavior at 0.15 μm gate length and, additionally, provide an excellent current driving-ability. Threshold voltage control is easy by optimizing the diffusion condition. We propose SPDC as a suitable process applicable to 0.2–0.1 μm BC p-MOSFET.

A theoretical derivation of the log-normal distribution of time-dependent dielectric breakdown in thin oxides: Yuh Yaw and R. S. Muller. Solid-St. Electron.32(7), 541 (1989)

A new process for a counter-doped region suitable for a 0.15 μm (gate length) buried channel (BC) pMOSFET is presented. At present serious short-channel effects of BC p-MOSFETs are recognized broadly as prohibitive for application at 0.1 μm. In order to realize 0.15 μm BC pMOSFETs, we propose a new process step, making use of a boron solid phase diffused channel (SPDC) from a Boron-doped silicate glass (BSG) to form an extremely shallow counter-doped region, which enables suppression of short-channel effects. Devices fabricated in this way exhibit good short-channel behavior at 0.15 μm gate length and, additionally, provide an excellent current driving-ability. Threshold voltage control is easy by optimizing the diffusion condition. We propose SPDC as a suitable process applicable to 0.2–0.1 μm BC p-MOSFET.