Superjunction MOSFET Research Articles

A Critical Analysis and Comparison of the Effect of Source Inductance on 3- and 4-Lead SuperJunction MOSFETs Turn-Off

This paper critically compares the turn-off performance of two package solutions, 3-lead (3L) vs. 4-lead (4L), in SuperJunction MOSFETs. It is commonly assumed that the better performance (lower switching losses) of the 4L MOSFET is obtained thanks to the decoupling of the power and driving loops. On the contrary, in this work, the experimental results, circuit models and Kirchhoff laws show that the turn-off improvement (lower turn-off losses) obtained by adopting the Kelvin source is due to the lower inductance of the driver loop of the 4L MOSFET, instead of the decoupling between the driver and power loops. In detail, an inductor is added to the gate path of the 4L MOSFET to obtain a total inductance in the driver loop equal to the 3L counterpart. The experimental results show that the 4L MOSFET presents the same drain current slew rate under this condition, although the driver and power loops are still decoupled.

Bipolar to unipolar conversion in superjunction MOSFETs during resonant switching

Superjunction MOSFETs have been one of the promising switching components for realizing resonant converters. In spite of the numerous studies about the resonant converters in power electronics, the detailed current flow in the device has been still unclear, especially for the inner-current circulation between the body diode and the MOSFET. By employing five-terminals on the superjunction MOSFET, mixed-mode half-bridge resonant converter is simulated. During the turn-on of the MOSFET, the gate charging current flows into the drain-to-source capacitance to form a built-in depletion of the pillars. In the case of the turn-off, the source current reversely flows across the channel with a slightly negative drain-to-source bias and diverts to the gate discharging current.

Gamma Ray on Superjunction MOSFET and Gate Ringing

Gamma Ray on Superjunction MOSFET and Gate Ringing

A Novel Deep-Trench Super-Junction SiC MOSFET with Improved Specific On-Resistance.

In this paper, a novel 4H-SiC deep-trench super-junction MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) with a split-gate is proposed and theoretically verified by Sentaurus TCAD simulations. A deep trench filled with P-poly-Si combined with the P-SiC region leads to a charge balance effect. Instead of a full-SiC P region in conventional super-junction MOSFET, this new structure reduces the P region in a super-junction MOSFET, thus helping to lower the specific on-resistance. As a result, the figure of merit (FoM, BV2/Ron,sp) of the proposed new structure is 642% and 39.65% higher than the C-MOS and the SJ-MOS, respectively.

SiC Super-Junction MOSFET robustness assessment and method to improve avalanche capability

In this paper, the reliability of super-junction MOSFET under single-pulse Unclamped Inductive Switching (UIS) was simulated using Sentaurus TCAD software. Through simulation of etching source metal, it was proved that the conduction of parasitic bipolar transistor in parallel multi-cell structure is the main cause of temperature concentration leading to burnout. The method of reinforcing super-junction MOSFET is proposed by using the conduction of parasitic transistors as the criterion for evaluating UIS performance. In the proposed two-layer alternating PN column stack structure, the upper PN columns have a charge imbalance structure with a higher p-column concentration than the n-column. The simulation results show that the improved structure has higher avalanche energy and wider process variation range compared to the traditional structure. Compared with the traditional device, the improved device achieves a continuous avalanche duration of 1.3 × 10−3 s and an avalanche robustness of 8.24 joules (J) when the parasitic bipolar transistor is non-conductive, significantly reducing the process difficulty by increasing the P-base concentration deviation to 5.8 × 1017 cm−3 under the same avalanche duration range.

The correlation of the drain-source capacitance variation and the P-pillar structures in a 4H-SiC quasi super junction MOSFET

In order to improve the trade-off between the 4H-SiC planar Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) and super junction MOSFET (SJ-MOSFET), particularly on the drain to source capacitance (Cds) which affects the switching performance, this study investigates the Cds of the quasi SJ-MOSFETs with various P-pillar widths, depths, and concentrations. The measured results show (1) when the N-type region between the P-pillars (Epi-1 region) is fully depleted, the Cds value abruptly drops, (2) when the N-type drift region beneath the P-pillar (Epi-2 region) is fully depleted, the slope of the Cds-Vds curve slowly changes because of the small extension of the depletion region in the P-type region. This is because the wider P-pillar width will increase the magnitude of the abrupt drop of the Cds and make the drop occur earlier; the abrupt drop of the Cds will occur later and the magnitude increases when the P-pillar depth is deeper due to the larger P-type region; Moreover, increasing the P-pillar concentration not only initiates the abrupt drop earlier and increases the magnitude, but also increases the minimum saturation value of the Cds at a higher reverse bias. This study also reveals that the mechanism of the Cds formation in a quasi SJ-MOSFET is different from the planar MOSFET and SJ-MOSFET. Finally, the simulated results are used to validate the influence of the P-pillar structures on the Cds – Vds curves in a quasi SJ-MOSFET.

SiC superjunction MOSFET with Schottky diode for improving short-circuit and reverse recovery ruggedness

In this article, a novel SiC superjunction MOSFET with Schottky diode containing N- and P-type barrier is proposed to improving short-circuit and reverse recovery ruggedness, investigated by TCAD simulations. The adoption of superjunction and p-shields structure can reduce saturation current, and thus, improve short-circuit capability. A fine gate oxide providing long-term reliability of the device is obtained. Also, N-type Schottky diode for electrons is used to dampen bipolar conduction of the parasitic body diode, while P-type Schottky diode for holes is introduced to constrain the hole inflow and extraction attributed to the transient variation of the superjunction. As a result, compared with an SBD-wall-integrated trench MOSFET (SWITCH-MOS), a low on-resistance and high breakdown voltage of the proposed structure are gained. More importantly, the proposed device exhibits stronger temperature-dependent immunity. As expected, simulation results indicate that the proposed device under 10 nH stray inductance shows a 30%–50 % reduction in the peak reverse recovery current and a 50%–70 % decrease in the current rising slope of reverse recovery, compared to only a single superjunction, when the metal workfunction varies from 5.1 to 5.6 eV. Moreover, the short-circuit withstanding time of the proposed structure increases roughly 2 times longer than that of SWITCH-MOS.

Comparison of 1.2 kV SiC Superjunction MOSFETs Formed by Multi-epitaxial Growth and Trench-filling Epitaxial Growth

Comparison of 1.2 kV SiC Superjunction MOSFETs Formed by Multi-epitaxial Growth and Trench-filling Epitaxial Growth

Impact of parasitic elements on the power dissipation of Si superjunction MOSFETs, SiC MOSFETs, and GaN HEMTs

In power conversion systems, where higher switching frequencies are required for miniaturization, the selection of power switches with lower power loss becomes essential for achieving better efficiency. At higher switching frequencies, the parasitic elements of the power switch largely dictate the efficiency of the power electronic system. Hence, it becomes critical to investigate the impact of parasitic losses on overall efficiency. The parasitic components of the power transistor vary with the semiconductor technology and thus effects the power converter system differently. This paper compares three power switch technologies: Silicon (Si) based Superjunction (SJ) power MOSFET, Silicon Carbide (SiC) based power MOSFET, and Gallium Nitride (GaN) based HEMT, for three different voltage ratings: 650 V, 900 V, and 1200 V. The effect of the parasitic components on the converter efficiency has been demonstrated using an inductive clamped loading circuit implemented in LTSPICE. The results demonstrate that at a frequency of 200 kHz, the total power loss for 650 V power switches was 44 W, 108 W, and 127 W for GaN, SiC, and SJ, respectively. At 500 kHz, the total power loss for 1200 V power switches was 622 W and 720 W for GaN and SiC, respectively. Overall, the GaN technology provides lower power losses than SiC and SJ due to lower parasitic capacitance and on-resistance, indicating the potential of GaN power devices for higher voltage applications. This comparison enables a power engineer to select an appropriate power switch that ensures the best possible efficiency for a specific application.

Study on the C OSS Dynamic Loss of Superjunction MOSFETs in Quasi-Resonant Flyback Converters

Study on the <i>C</i> _OSS Dynamic Loss of Superjunction MOSFETs in Quasi-Resonant Flyback Converters

Impact Analysis of Off-State Avalanche-Breakdown Stress on 650 V-Class Superjunction MOSFET

In this work, the reliability degradation of a 650 V-class superjunction (SJ) MOSFET under continuous violent OFF-state avalanche-breakdown stress is studied. Decreased threshold voltage and increasing saturation current have been observed which are attributed to the injection of hot holes below the trench bottom into the gate oxide layer. High-energy electrons and holes are generated under OFF-state avalanche stress leading to accelerated and violent collision ionization. The body diode suffers from severe avalanche breakdown leading to heat generation by collision ionization. In addition, the injection of hot holes is further enhanced with the assistance of the electrical field at the bottom of the gate. These phenomena are further analyzed by experimental characterizations and theoretical simulation using TCAD tools. Our comprehensive study on the reliability degradation behaviors of SJ devices under OFF-state avalanche-breakdown stress can be instructive in future device optimization and failure analysis.

A Novel Super-junction MOSFET with Enhanced Switching Performance and Ruggedness

In this paper, a novel super-junction (SJ) MOSFET with enhanced switching performance and ruggedness is proposed and investigated by the method of TCAD simulations. An N+/P- polysilicon junction gate electrode and separation layer between P-base and P-pillar are introduced to the trench SJ-MOSFET. For the N+/P- junction trench gate, the P- polysilicon located in the bottom of the trench plays the role of insulating layer, which efficiently reduces the gate charge (QG), thus increasing the switching speed and reducing the switching loss. The P-pillar does not contact with P-base so a depletion region is formed and the gate to drain charge (QGD) is reduced. Besides, the specific separation layer also inhibits the activation of the parasitic bipolar transistor (BJT) to improve the unclamped inductive switching (UIS) capability. The results of the simulation reveal that the proposed SJ-MOSFET is better in switching performance and ruggedness.

Superjunction Reliability Analysis Under Extreme High Positive and Negative Gate Voltage Stress

High gate stress test is an extremely important part of power device reliability test. On this basis, a 650 V super junction device is designed and fabricated, conventional stress test including high temperature gate bias (HTGB), high temperature reverse bias (HTRB) test results show that the device possess good reliability. The degradation of performance parameters under extreme high gate stress (including positive and negative) and the corresponding mechanism is further studied. It is found that the main performance parameters of superjunction MOSFET (SJ-MOSFET) will change significantly when the gate voltage stress is greater than 70 V. Under the positive high gate voltage stress, the threshold voltage decreases significantly. Under the negative high gate voltage stress, the threshold voltage also shifted to the left. Comparing the device under the same value of positive and negative high gate stress, it is found that the degradation degree of the device under positive stress is far greater than that under negative stress. Theoretical analysis combined with experimental data believes that the two degradation mechanisms are different. For positive stress, tunneling electrons collide on their way to the gate electrode creating electron–hole pairs, and the holes are captured by traps. But for negative gate voltage, holes tunnel and serve as extra gate positive charge directly. The electron injection efficiency is much higher than hole injection efficiency. Besides, the n-type region is larger at the bottom of the gate. Simultaneously, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{C}$</tex-math> </inline-formula> – <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{V}$</tex-math> </inline-formula> measurement is also taken to prove the hypothesis.

A Novel Structure of Super-junction MOSFET with Improved Avalanche Energy Capability

The UIS characteristic of the device is a key parameter of the super-junction MOSFET, which represents the reliable performance of the device in the face of extreme conditions. The maximum avalanche energy (EAS ) that the device can withstand under a single pulse of the gate electrode or the maximum avalanche energy (EAR ) that the device can withstand under multiple pulses of the gate electrode is commonly used in the industry to characterize the UIS characteristic. To solve the avalanche energy problem of super-junction MOSFET, we propose a novel structure of super-junction MOSFET with a P-type diffused region on the top of the N-column drift region.

Impact of Temperature on Neutron Irradiation Failure-in-Time of Silicon and Silicon Carbide Power MOSFETs

Accelerated neutron tests on silicon (Si) and silicon carbide (SiC) power MOSFETs at different temperatures and drain bias voltages were performed at the ChipIr facility (Didcot, UK). A super-junction silicon MOSFET and planar SiC MOSFETs with different technologies made by STMicroelectronics were used. Different test methods were employed to investigate the effects of temperature on neutron susceptibility in power MOSFETs. The destructive tests showed that all investigated devices failed via a single-event burnout (SEB) mechanism. Non-destructive tests conducted by using the power MOSFET as a neutron detector allowed measuring the temperature trend of the deposited charge due to neutron interactions. The results of the destructive tests, in the −50 °C–180 °C temperature range, revealed the lack of a common trend concerning the FIT temperature dependence among the investigated SiC power MOSFETs. Moreover, for some test vehicles, the FIT-temperature curves were dependent on the bias condition. The temperature dependence of the FIT values, observed in some SiC devices, is weaker with respect to that measured in the Si MOSFET. The results of the non-destructive tests showed a good correlation between the temperature trends of the deposited charge with those of FIT data, for both Si and SiC devices.

A Review of Power Electronic Devices for Heavy Goods Vehicles Electrification: Performance and Reliability

This review explores the performance and reliability of power semiconductor devices required to enable the electrification of heavy goods vehicles (HGVs). HGV electrification can be implemented using (i) batteries charged with ultra-rapid DC charging (350 kW and above); (ii) road electrification with overhead catenaries supplying power through a pantograph to the HGV powertrain; (iii) hydrogen supplying power to the powertrain through a fuel cell; (iv) any combination of the first three technologies. At the heart of the HGV powertrain is the power converter implemented through power semiconductor devices. Given that the HGV powertrain is rated typically between 500 kW and 1 MW, power devices with voltage ratings between 650 V and 1200 V are required for the off-board/on-board charger’s rectifier and DC-DC converter as well as the powertrain DC-AC traction inverter. The power devices available for HGV electrification at 650 V and 1.2 kV levels are SiC planar MOSFETs, SiC Trench MOSFETs, silicon super-junction MOSFETs, SiC Cascode JFETs, GaN HEMTs, GaN Cascode HEMTs and silicon IGBTs. The MOSFETs can be implemented with anti-parallel SiC Schottky diodes or can rely on their body diodes for third quadrant operation. This review examines the various power semiconductor technologies in terms of losses, electrothermal ruggedness under short circuits, avalanche ruggedness, body diode and conduction performance.

A Modeling of 4H-SiC Super-Junction MOSFETs with Filtered High Energy Implantation

In this paper, the modeling of SJ-MOSFETs beyond the voltage class of 3.3 kV simulated with verified deep aluminum box-like shaped profiles by using TCAD simulation is described. The simulation results are used to investigate the influence of ion implantation parameters on electrical characteristics. For the formation of pillar regions, high energy implantation is performed through energy filter with a multi epitaxial growth method using a patterned mask. While high thickness of epitaxial layer is indispensable for obtaining a high blocking capability, it is revealed that the optimization of doping concentration of p-pillar and drift layer parameters yields similar on-state-resistance by charge compensations of SJ-structure.

Considerations for SiC super junction MOSFET: On-resistance, gate structure, and oxide shield

SiC super junction (SJ-) MOSFETs have recently gained attention due to their potentially low on-resistance (RON). In this paper, we conduct TCAD numerical simulations to study SiC non-SJ-MOSFETs, planar-gate (P-) SJ-MOSFETs, and trench-gate (T-) SJ-MOSFETs with voltage levels ranging from 1.5 kV to 15 kV. We focus on the design considerations for SiC SJ-MOSFETs, including on-resistance, gate structure, and oxide shield. Our results reveal that SiC SJ-MOSFETs are suitable for higher voltage level applications (5.5 kV or beyond), unlike non-SJ-MOSFETs, which exhibit extremely high increasing drift resistance with voltage level. The simulations suggest that the T-SJ-MOSFET achieves lower RON than the P-SJ-MOSFET, mainly due to the narrower p/n pillar in the trench structure, rather than higher channel density. Additionally, it is necessary to fabricate a p-shield in the T-SJ-MOSFET to reduce the oxide field and increase the switching speed. While the gate structure (planar gate or trench gate) has been a focused research topic for non-SJ-MOSFETs, our study highlights the importance of considering the gate structure for SJ-MOSFET design as well.

Gate Ringing in Superjunction MOSFETs with a Parasitic Capacitance in the Load Inductor

Gate Ringing in Superjunction MOSFETs with a Parasitic Capacitance in the Load Inductor

Effects of ion implantation process on defect distribution in SiC SJ-MOSFET

A superjunction (SJ) structure in power devices is compatible with low specific on-resistance and high breakdown voltage. To fabricate the SJ structure in SiC power devices, the repetition of ion implantation and epitaxial growth processes is a practical method. However, the impact of ion implantation on device performance has rarely been reported. In this study, we measured the carrier lifetime distributions in a SiC MOSFET with an SJ structure using a microscopic free carrier absorption method. Furthermore, we observed the distribution of defects via cathodoluminescence and deep levels via deep-level transient spectroscopy. We observed that Al ion implantation induced defects and reduced the carrier lifetime in the SJ structure. However, N ion implantation does not significantly induce defects. Additionally, Al ion implantation at room temperature exhibited more significant effects than implantation at 500 °C. The results can aid in controlling the carrier lifetime in SiC SJ MOSFETs.