Considerations for SiC super junction MOSFET: On-resistance, gate structure, and oxide shield

Abstract

SiC super junction (SJ-) MOSFETs have recently gained attention due to their potentially low on-resistance (RON). In this paper, we conduct TCAD numerical simulations to study SiC non-SJ-MOSFETs, planar-gate (P-) SJ-MOSFETs, and trench-gate (T-) SJ-MOSFETs with voltage levels ranging from 1.5 kV to 15 kV. We focus on the design considerations for SiC SJ-MOSFETs, including on-resistance, gate structure, and oxide shield. Our results reveal that SiC SJ-MOSFETs are suitable for higher voltage level applications (5.5 kV or beyond), unlike non-SJ-MOSFETs, which exhibit extremely high increasing drift resistance with voltage level. The simulations suggest that the T-SJ-MOSFET achieves lower RON than the P-SJ-MOSFET, mainly due to the narrower p/n pillar in the trench structure, rather than higher channel density. Additionally, it is necessary to fabricate a p-shield in the T-SJ-MOSFET to reduce the oxide field and increase the switching speed. While the gate structure (planar gate or trench gate) has been a focused research topic for non-SJ-MOSFETs, our study highlights the importance of considering the gate structure for SJ-MOSFET design as well.