Superjunction MOSFET Research Articles

Performance and Reliability Review of 650 V and 900 V Silicon and SiC Devices: MOSFETs, Cascode JFETs and IGBTs

The future of power conversion at low-to-medium voltages (around 650 V) poses a very interesting debate. At low voltages (below 100 V), the silicon (Si) MOSFET reigns supreme and at the higher end of the automotive medium-voltage application spectrum (approximately 1 kV and above) the SiC power MOSFET looks set to topple the dominance of the Si insulated-gate bipolar transistor (IGBT). At very high voltages (4.5 kV, 6.5 kV and above) used for grid applications, the press-pack thyristor remains undisputed for current source converters and the press-pack IGBTs for voltage source converters. However, around 650 V, there does not seem to be a clear choice with all the major device manufacturers releasing different technology variants ranging from SiC Trench MOSFETs, SiC Planar MOSFETs, cascode-driven WBG FETs, silicon NPT and Field-stop IGBTs, silicon super-junction MOSFETs, standard silicon MOSFETs, and enhancement mode GaN high electron mobility transistors (HEMTs). Each technology comes with its unique selling point with gallium nitride (GaN) being well known for ultrahigh speed and compact integration, SiC is well known for high temperature, electro-thermal ruggedness, and fast switching while silicon remains clearly dominant in cost and proven reliability. This article comparatively assesses the performance of some of these technologies, investigates their body diodes, discusses device reliability, and avalanche ruggedness.

Theory of 3-D Superjunction MOSFET

The state-of-the-art superjunction (SJ) MOSFETs are based on the p-n pillar structures, arranged in a 2-D stripe geometry. This arrangement uses the superposition of the electric field components at the p-n junctions to create an enhanced depletion volume for higher breakdown capability. In this article, we will discuss structures, which additionally use the component of the electric field in the third dimension, to further enhance the depletion space. This allows higher doping concentrations in the pillars, which result in a better tradeoff between the breakdown voltage and the ON-state resistance, when compared with the 2-D structures. Specifically, we present a core–shell cylindrical SJ structure, and using the radial Poisson equation, we explain the electric field distribution within the SJ. We further discuss which geometry (core or shell) gives the best performance tradeoff. This is followed by the development of an analytical model, for the ON-state resistance in a 3-D SJ. Finally, we derive a specific figure of merit for the 3-D SJs and compare it with that of the equivalent 2-D structures.

Optimal Dead-Time Control Scheme for Extended ZVS Range and Burst-Mode Operation of Phase-Shift Full-Bridge (PSFB) Converter at Very Light Load

Phase-shift full-bridge (PSFB) converter is a widely used topology for high-efficiency and high-power applications, thanks to low voltage/current stress of all components and zero-voltage-switching operation of primary mosfet s. The critical drawback of the PSFB converter is hard-switching characteristics of primary mosfet s at a very light load, which causes severe thermal explosion and extremely high input power consumption, especially with the latest super-junction mosfet . To minimize the switching loss of the PSFB converter at a very light load, a new optimal dead-time control scheme with burst-mode operation is proposed in this paper and its validity is verified experimentally with the implemented 2.2-kW server power supply unit.

A Low Reverse Recovery Charge Superjunction MOSFET With an Integrated Tunneling Diode

A superjunction MOSFET with an integrated tunneling diode is proposed and investigated by simulations in this article. The tunneling diode comprised the N+ region and the P+ region on the surface of the P-base region is connected in series with the P+/P-pillar/N+ (sub) diode isolated by an oxide layer. The electrons are prevented from injecting into the P-pillar region from both the N-pillar region and the N+ (sub) region, which leads to a low reverse recovery charge in the proposed device. As a result, up to 72.2% and 74.1% reduction in the reverse recovery charge could be achieved when compared with the conventional one at 300 and 400 K, respectively.

A Vertical Superjunction MOSFET With n-Si and p-3C-SiC Pillars

A vertical superjunction (SJ) MOSFET with n-Si and p-3C-SiC pillars is introduced. Since 3C-SiC has $4\times $ higher breakdown electric field than Si, the sensitivity of the breakdown voltage ( ${V}_{\text {B}}$ ) to charge imbalances is weakened, which helps to improve the tradeoff between the specific ON -resistance ( ${R}_{ \mathrm{\scriptscriptstyle ON},\text {sp}}$ ) and ${V}_{\text {B}}$ . In addition, since the n-Si/p-3C-SiC junction stays off at the ON -state of the body diode and the hole mobility in 3C-SiC is low, the reverse recovery charge ( ${Q}_{\text {rr}}$ ) is reduced and the resistance of the p-pillar is increased, which suppresses electric oscillations during reverse recovery. With the optimum design, the proposed SJ MOSFET obtains a 2%–11% lower ${R}_{ \mathrm{\scriptscriptstyle ON},\text {sp}}$ than the conventional SJ MOSFET. Numerical simulation results of 600-V designs show that the proposed SJ MOSFET has a 7% lower ${R}_{ \mathrm{\scriptscriptstyle ON},\text {sp}}$ , a 39% lower ${Q}_{\text {rr}}$ , and much smaller electric oscillations during reverse recovery compared to the conventional SJ MOSFET.

A Novel Kilovolts GaN Vertical Superjunction MOSFET With Trench Gate: Approach for Device Design and Optimization

In this paper, a gallium nitride (GaN) vertical superjunction (SJ) MOSFET with trench gate is proposed and studied by the TCAD simulation. In order to achieve the typical electric field ( $E$ -field) modulation effect by the P+/N/N+ structure in the conventional Si SJ-MOS, the P-GaN/unintentional doped (UID)-GaN/N+-GaN stack is alternatively used by taking into account the unavailability of P+-GaN. In this manner, the P-GaN and N+-substrate serve as the field-stop (FS) layers in the proposed GaN SJ-MOS. In the forward bias, the enhancement-mode function of the device is enabled by the gated side-wall and aperture composite channel that leads to a 1.47-V threshold voltage of the device. In the reverse bias, the breakdown of the device is governed by two mechanisms: 1) the punchthrough (PT) in the top P-GaN/N-drift junction due to the possible under design of the P-GaN thickness; 2) the avalanche breakdown triggered by high $E$ -field due to the possible under design of the bottom UID-GaN thickness. Hence, from the uniform $E$ -field distribution point of view, a device optimization approach for GaN vertical SJ-MOS is proposed. The hole and electron densities of P-GaN and N-drift are optimized to achieve a uniform $E$ -field distribution in the device both in the lateral and vertical directions, which is found to be $6 \times 10^{16}$ cm $^{-3}$ . Moreover, the thickness ratio of P-GaN/UID-GaN is designed to obtain an identical intrinsic breakdown for the top P-GaN/N-drift junction and bottom UID/N-drift region, which enables the maximum Baliga’s figure-of-merit (BFOM) of the device. The concept of device design and optimization is of great interests for GaN vertical device for over kilovolts applications.

Robustness and reliability review of Si and SiC FET devices for more-electric-aircraft applications

Increased electrification of traditionally hydraulic and pneumatic functions on aircrafts has put power electronics at the heart of modern aviation. Aircraft electrical power systems have traditionally operated at 115 V AC and 28 V DC with a constant speed generator and transformer rectifier units converting jet engine power into electrical power. However, due to the increasing trend towards the More Electric Aircraft (MEA), 270 V DC systems are likely in the future. This calls into question, the power semiconductor device technology that enables the on-board power converters needed for electro-mechanical actuation as well as solid-state circuit breakers for system protection. Silicon IGBTs have been the work-horse of power electronics, but as switching speeds increase due to the need for high frequency operation, the bipolar nature of IGBT tail currents become a limiting factor for improved energy conversion efficiency. A number of unipolar FET technologies, including SiC trench MOSFETs, SiC planar MOSFETs, silicon super-junction MOSFETs and SiC JFETs in cascode with a low voltage Si MOSFET, have become commercialized at around 650 V. However, reliability and robustness, especially against single event burn-out and/or single event gate rupture is critical. This paper experimentally investigates the performance of the listed FET devices under Unclamped Inductive Switching and Bias Temperature Instability/gate oxide stress tests.

Analysis and optimization of the switching noise for Super-junction MOSFET in full bridge converter system

In this paper, the switching noise of Super-junction MOSFET in full bridge converter system has been investigated. According to the experimental results, the largest noise is induced by the steep reverse recovery current variation (dirr/dt) during the Super-junction MOSFET body diode reverse recovery. In order to understand the phenomena, the TCAD simulations and analyses have been carried out. It is found that the reverse recovery currents in the cell region and the termination region combine to result in the steep dirr/dt. The current in cell region aggravates the current variation, however, the current in termination region contributes to alleviate the current variation. Furthermore, it is also shown that increasing the hole injection level in termination region can alleviate the dirr/dt, and then the switching noise is reduced effectively. Finally, an optimized structure with heavily doped main junction in the termination region is proposed for the SJ-MOSFET, which can increase the hole injection efficiency greatly to reduce the switching noise during the Super-junction MOSFET body diode reverse recovery.

Study on the Intrinsic Origin of Output Capacitor Hysteresis in Advanced Superjunction MOSFETs

The output capacitor ${C}_{\text {OSS}}$ of the superjunction (SJ) MOSFET extracted from large-signal measurements has recently been found to have hysteresis characteristic. This letter reveals the intrinsic origin of ${C}_{\text {OSS}}$ hysteresis in advanced SJ MOSFETs with the help of numerical simulations. The results show that the extracted hysteresis area of ${C}_{\text {OSS}}$ is influenced by $\textit {dV}_{\text {DS}}/\textit {dt}$ and changes with the excitation voltage wave. Different transient ${C}_{\text {OSS}}$ extracted at the same ${V}_{\text {DS}}$ during the charge process and the discharge process are shown to be rated to different depletion boundary widths, and the root cause is the finite velocities of carriers in semiconductor.

Fabrication of a 650V Superjunction MOSFET With Built-in MOS-Channel Diode for Fast Reverse Recovery

In this letter, a 650V superjunction (SJ) MOSFET with a built-in MOS-channel diode for fast reverse recovery is proposed and fabricated. Simulations on the new device via Sentaurus TCAD are first made. For the proposed device, a body contact is employed to restrain the parasitic PN diode and the reverse recovery characteristics can be modulated by varying the body contact width. The proposed device with $1~\mu \text{m}$ -width body contact has been fabricated and tested. According to measurement results, peak reverse recovery current density ( $\text{j}_{\text {PR}}$ ) of the proposed SJ MOSFET (34.1A/cm2) is 25.2% lower than the conventional SJ MOSFET (45.6A/cm2). Reverse recovery energy loss ( $\text{E}_{\text {rr}}$ ) of the proposed SJ MOSFET is 0.94mJ/cm2 and is 39.4% lower than the conventional SJ MOSFET (1.55mJ/cm2). The specific on-resistance of the proposed device (18.2 $\text{m}\Omega \cdot \text {cm}^{\text {2}}$ ) is slightly higher than the counterpart SJ MOSFET (17.1 $\text{m}\Omega \cdot \text {cm}^{\text {2}}$ ) because of lower active MOS-gate density. However, input capacitor ( $\text{C}_{\text {iss}}$ ) and gate charge ( $\text{Q}_{\text {G}}$ ) of the proposed SJ MOSFET are reduced a lot for less active MOS-gates.

Superjunction MOSFET With Dual Built-In Schottky Diodes for Fast Reverse Recovery: A Numerical Simulation Study

A new superjunction MOSFET (SJ-MOSFET) architecture with dual built-in Schottky diodes is proposed and studied with the numerical TCAD simulations. This letter is based on silicon. One Schottky contact is formed at the top of the n-pillar, while the other is formed at the bottom of the p-pillar. During the reverse conduction period, the Schottky junctions turn on at a lower voltage than the PN junction. The current flows through n-pillar and p-pillar in parallel, so the potential difference across the PN junction is kept below its turn-on voltage. Thus, minority carrier injection through the PN junction is completely suppressed, leading to a superior reverse recovery performance. Integration of a single Schottky contact to either the n-pillar or the p-pillar cannot completely suppress the turn-on of the PN junction in the SJ-MOSFET due to the potential drop created by the current through only one type of the pillars. Furthermore, the proposed dual-Schottky SJ-MOSFET reduces the gate charge ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${Q} _{\mathrm {G}}$ </tex-math></inline-formula> ) and the gate-to-drain charge ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${Q} _{\mathrm {GD}}$ </tex-math></inline-formula> ), compared with the conventional SJ-MOSFET, leading to better figures of merit.

A Three-Phase Grid-Connected Inverter Equipped With a Shunt Instantaneous Reactive Power Compensator

This paper introduces a three-phase grid-connected inverter for commercial-scale photovoltaic systems. The circuit topology combines an ac-inductor-less active bridge with a parallel-connected pulsewidth modulation inverter acting as an instantaneous reactive power compensator. The active bridge, called a 120° conduction inverter, operates at a switching frequency equal to the grid frequency and outputs a 120° rectangular current, while the compensator eliminates the harmonic currents included in the rectangular current. The main advantage of this strategy is the reduction in size of the required ac inductor by a factor of 4, as well as the reduction of power losses in the switching devices. The theoretical analysis clearly shows that the compensator can synthesize a sinusoidal output current by controlling only instantaneous reactive power, thus eliminating the need for electrolytic capacitors. A 5-kW experimental setup validates the operating principle and the control method of the proposed inverter and exhibits an inverter efficiency as high as 99.2% with Si superjunction mosfet s.

Scaling and optimisation of lateral super-junction multi-gate MOSFET for high drive current and low specific on-resistance in sub–50 V applications

The scaling of a non-planar super-junction (SJ) Si MOSFET based on SOI technology for low voltage rating applications (below 50 V) requires a subsequent optimisation of SJ unit. The scaling and the SJ optimisation are carried out with physically based commercial TCAD device simulations by Silvaco. The study is based on a meticulous calibration of drift-diffusion simulations against experimental characteristics of a 1 μm gate length SJ multi-gate MOSFET (SJ-MGFET) aiming at improving density, switching speed, drive current, breakdown voltage (BV), and specific on-resistance (Ron,sp). We investigate scaling of the device architecture to improve the device performance by optimising doping profile to achieve an avalanche-enabled device under a charge balanced condition. The optimised SJ-MGFETs scaled by a factor of 0.5 and 0.25, with a folded alternating U-shaped n/p-SJ drift region pillar of a width of 0.3 μm and a trench depth of 2.7 μm, achieve a low specific on-resistance (Ron,sp) of 7.68 mΩ⋅mm2 and 2.24 mΩ⋅mm2 (VGS = 10 V) and BV of 48 V and 26 V, respectively. The scaled 0.5 μm and 0.25 μm gate length SJ-MGFETs offer a transconductance (gm) of 20 mS/mm and 56 mS/mm at a drain voltage of 0.1 V, respectively, greatly improving the levels of integration in a CMOS architecture.

Analytic Model of Specific ON-State Resistance for Superjunction MOSFETs With an Oxide Pillar

An analytical model for superjunction (SJ) MOSFETs having an oxide pillar between the n-pillar and the p-pillar is developed. Owing to the low permittivity of the oxide, a high electric field is sustained across the oxide. This reduces the parasitic depletion width within the n-pillar, thus improving the current conducting path. The advantage of this structure is particularly visible as the cell pitch is scaled down and the pillows become narrower. The use of an oxide pillar leads to 30% reduction in the specific ON-state resistance when compared to a conventional SJ for a 2- $\mu \text{m}$ cell pitch. The analytical model shows a good agreement with the simulation results.

A Simulation Study of a Novel Superjunction MOSFET Embedded With an Ultrasoft Reverse-Recovery Body Diode

In this paper, a novel superjunction (SJ) MOSFET embedded with an ultrasoft reverse-recovery body diode is proposed and studied by simulation. The device has a composite assistant layer, which consists of a highly doped n-buffer region and an extended p-pillar region, under the SJ layer. The assistant layer provides residual carriers during the reverse-recovery procedure and smoothens the current. Simulated results show that the soft factor is upgraded from 0.04 to over 0.3 when the depth of the assistant layer increases from $0~\mu \text{m}$ to that of the SJ layer. The increment of the specific ON-resistance is less than 10% if the concentration of the n-buffer region is 25 fold that of the n-pillar region.

Design and Optimization of SiC Super-Junction MOSFET Using Vertical Variation Doping Profile

In this paper, uniformly doped drift region of silicon carbide (SiC) super-junction (SJ) MOSFET is replaced with vertical variable doping profile (VVD) to achieve a better tradeoff between breakdown voltage (BV) and specific ON-resistance ( ${R}_{\text {sp,on}}$ ). While it is known that the SJ device consists of two vertical columns of n- and p-type, SJ VVD feature lies in increasing the doping concentration from top to bottom in the N-column and vice-versa in the P-column within the drift region. The proposed SJ VVD allows $\text {R}_{{\text {sp, on}}}$ to reduce further due to increased average doping concentration in conducting N-column and BV to increase further due to shifting of an electric field from corners to the center of the drift region. BV and ${R}_{\text {sp,on}}$ improved by 10% in an SJ VVD MOSFET and these parameters follow linear relationship similar to SJ MOSFET. The 2-D numerical simulations from Synopsys TCAD are used for investigating the static and dynamic characteristics of the device. In addition to 30% improvement in Baliga figure of merit, 35% improvement is obtained over SJ MOSFET in turn on and turn off switching energies for a clamped inductive circuit at 1200 V–20 A. Improved dynamic characteristics of SJ VVD can be attributed to reduction in gate charge ( ${Q}_{g}$ ) and miller capacitance ( ${c}_{\text {rss}}$ ) compared to SJ MOSFET.

Improving the Third Quadrant Operation of Superjunction MOSFETs by Using the Cascode Configuration

In this paper, the third quadrant behavior of a high-voltage superjunction mosfet (SJ-FET) in cascode configuration (CC) with a low-voltage silicon mosfet is deeply studied by means of an analytical model and experimental data. The third quadrant dynamic behavior of the SJ-CCs is compared to the standalone counterparts by evaluating their reverse recovery time (tRR), reverse recovery peak current (IRRM), and reverse recovery charge (QRR). An analytical model and experimental results show that the SJ-CC avoids or mitigates the activation of the SJ-FET body diode during the third quadrant operation. As a consequence, the SJ-CC strongly improves the widely used figure-of-merit RON·QRR, which considers the on -state resistance of the transistors (RON). In addition, the results obtained using an SJ-CC are similar or better than those achieved by SJ-FETs with enhanced reverse recovery (i.e., irradiated SJ-FETs). This paper also includes a comparison with commercial wide bandgap switches, concluding that the RON·QRR value provided by the SJ-CC is around eight times higher than that provided by a commercial GaN cascode.

Investigation on the Self-Sustained Oscillation of Superjunction MOSFET Intrinsic Diode

This paper presents the analyses on the self-sustained oscillation of superjunction MOSFET intrinsic diode. At first, the characteristics of the self-sustained oscillation for the superjunction MOSFET intrinsic diode are identified by the double-pulse switching test. The test results show that the self-sustained oscillation with significant self-amplification phenomenon can be triggered during the reverse recovery transient of superjunction MOSFET intrinsic diode. Based on the Sentaurus TCAD simulation, the self-sustained oscillation is reproduced. The simulation results reveal the root cause of the self-sustained oscillation. Due to the snappy reverse recovery of superjunction MOSFET intrinsic diode, the steep slope of diode snap off current can generate high voltage across the common source inductance, which drives the gate–source voltage and turns on the high-side MOSFET. The unexpected MOSFET turn-on can, in return, enhance the steepness of the current slope when the diode snap off. This leads to a positive feedback process and self-sustained oscillation is generated. In the end, based on the theoretical analyses and experimental results, the necessary methods that can suppress the oscillation are presented.

On the Specific on-State Resistance of Superjunction MOSFETs With a Compensated Pillar

In this letter, we report an analytical model for the on-state characteristics of a superjunction (SJ) metal–oxide–semiconductor field effect transistor, featuring a compensated pillar between the n-pillar and the p-pillar. Since a large amount of lateral electric field is sustained in the compensated region, the doping concentration in the n-pillar can be enhanced significantly, leading to a substantial reduction in the on-state resistance of the SJ. Simulation results proved that the use of an extra compensated pillar within the SJ structure reduces the on-state resistance by 25% compared to that of a conventional SJ for the same breakdown voltage.

Optimisation of lateral super-junction multi-gate MOSFET for high drive current and low specific on-resistance in sub-100 V applications

The design and optimisation of a non-planar super-junction (SJ) Si MOSFET based on SOI technology for low voltage rating applications (below 100 V) is carried out with physically based commercial 3-D TCAD device simulations using Silvaco. We calibrate drift-diffusion simulations to experimental characteristics of the SJ multi-gate MOSFET (SJ-MGFET) aiming at improving drive current, breakdown voltage (BV), and specific on-resistance (Ron,sp). We investigate variations in the device architecture and improve device performance by optimizing doping profile under charge imbalance. The SJ-MGFET, using a folded alternating U-shaped n/p– SJ drift region pillar width of 0.3 μm with a trench depth of 2.7 μm achieves specific on-resistance (Ron,sp) of 0.21 mΩ.cm2 at a BV of 65 V. In comparison with conventional planar gate SJ-LDMOSFETs, the optimised SJ-MGFET gives 68% reduction in Ron,sp and 41% increase in a saturation drain current at a drain voltage of 5 V and a gate voltage of 10 V.