Successive Approximation ADC Research Articles

Retraction Note: A 9-bit pseudo-noise-based calibrated successive approximation ADC with differential/integral nonlinearity enhancement

Retraction Note: A 9-bit pseudo-noise-based calibrated successive approximation ADC with differential/integral nonlinearity enhancement

Inverter-based noise-shaping SAR ADC for low-power applications

Noise-Shaping (NS) Successive-Approximation (SAR) Analog-to-Digital Converters (ADCs) are one of the most heavily researched ADC topologies in recent years. This high attention is attributed to the advantages of the NS SAR architecture that combines the merits of ΣΔ and SAR converters. However, the implementation of the NS SAR loop-filter in a passive or an active form imposes challenging tradeoffs among power dissipation, adequacy for scaling with technology, performance, and robustness against process-voltage-temperature (PVT) variations. In this work, a NS SAR ADC realization, based on inverter-based amplification, is proposed that alleviates these design challenges. The proposed implementation is used to design two ADCs in 28 nm CMOS technology to demonstrate its effectiveness. The first ADC employs an active loop-filter and achieves a signal-to-noise-plus-distortion (SNDR) of 62.9 dB, at a sampling frequency of 90 MHz, and an oversampling ratio (OSR) of 4, while consuming 0.59 mW from a 0.9 V supply. The second ADC has a passive loop-filter and provides 61 dB of SNDR for the same OSR and sampling frequency, with 0.58 mW power dissipation.

The SparkPix-S ASIC for the sparsified readout of 1 MHz frame-rate X-ray cameras at LCLS-II: pixel design and simulation results

Exploiting the “sparse” nature of the information in XPCS (X-ray Photon Correlation Spectroscopy) and XSVS (Speckle Visibility Spectroscopy) experiments, we present the SparkPix-S, a 3-sides buttable Application Specific Integrated Circuit (ASIC) based on a sparsified readout strategy for large-format hybrid detectors. The SparkPix-S architecture, based on the successful ePix family, will be composed as follows: a front-end 2-D matrix of 384×352 square pixels with 50 µm pitch is arranged to match the dimensions of a PIN Si-sensor matrix; charge readout, signal shaping and amplitude discrimination is performed at pixel-level, by means of a low-power (<18 µW) analog processor, which, in case of an event, negotiates access to an analog bus placed every other column; on the chip periphery (balcony), the information on each bus is digitized by an array of successive approximation analog-to-digital converters (SAR-ADCs) running at 10 Msps; on the digital back-end the global logic will generate the output data stream using low-voltage differential signalling (LVDS).A first prototype of the SparkPix-S, with a reduced matrix size of 96×96 pixels, is currently under production on a 130 nm CMOS technology. Simulated performance results show an equivalent noise charge <60 el. r.m.s. at 1 MHz repetition rate, with a maximum input energy of 60 keV and capability to discriminate charge signals with equivalent energy as low as 900 eV.

A 1.2v ΔΣ ADC Modulator Using 4-bit SAR Quantizer for Biomedical Applications by using 65nm CMOS Technology

This research focuses on enhancing Sigma-Delta ADC modulators for biomedical applications by leveraging the working principle of Successive Approximation ADC circuits. The proposed modulator includes a comparator, DAC, successive approximation register, and control circuit. The operational process begins with the sample and holds circuit-initiating conversions by sampling the input signal, and then compared with the DAC output. Using a 4-bit example, the successive approximation register refines the DAC output through iterative bit adjustments until the closest digital code approximation to the input is voltage independent of input voltage, occurring incrementally one bit at a time. The proposed enhancement aims to optimize Sigma-Delta ADC modulator performance for biomedical applications, ensuring high resolution and speed. Typical conversion speeds range from 2 to 5 MSPS, with resolutions varying from 8 to 16 bits, contributing to improved precision and efficiency in capturing and digitizing biomedical signals.

Multi-channel and high-precision analog-to-digital converter chips for power grid detection

This project focuses on the research of high-precision multi-channel analog-to-digital converter chips for power grid detection and system applications. There have been breakthroughs made in a series of key technologies, such as successive approximation ADC architecture, oversampling ADC architecture, and digital calibration technology. By combining it with multi-channel ADC to achieve high-precision multi-channel analog-to-digital converter design, it provides strong support for China to achieve autonomous and controllable high-precision multi-channel ADC chips and has extremely high application value.

An offset and gain error calibration method in high-precision SAR ADCs

Successive approximation (SAR) ADC suffers from kinds of nonidealities such as offset and gain error which affect its absolute quantization range and reduce its performance in the high-precision applications. This paper presents a static offset and an embedded gain error calibration in analog domain, attempting to improve the conversion range error in SAR ADC architecture. The presented calibration technique reuses the CADC array, facilitating an analog-domain calibration within small dissipation.

A VTC/TDC-Assisted 4× Interleaved 3.8 GS/s 7b 6.0 mW SAR ADC With 13 GHz ERBW

Compact, high-bandwidth analog-to-digital converters (ADCs) with moderate resolution are a critical building block in high-speed communication links. In this work, a hybrid time and voltage domain ADC is presented that uses a single high-speed voltage-to-time converter (VTC) as a high-bandwidth sampling buffer for a four-way time-interleaved successive approximation (SAR) ADC. Time-domain encoding also enables a low-power 3b SAR assist time-to-digital converter (TDC) to enhance SAR speed with minimal calibration. A 0.0045 mm2 prototype fabricated in 22 nm fin field-effect transistor (FinFET) CMOS provides 13 GHz effective resolution bandwidth (ERBW) and consumes 6.0 mW with a Nyquist signal-to-noise-and-distortion ratio (SNDR) of 38 dB at 3.8 GS/s, for 24.4 fJ/step Walden FoM.

Design and Simulation of 4 bit- Successive Approximation ADC

Design and Simulation of 4 bit- Successive Approximation ADC

Design of a 12 bit SAR ADC with Self-Calibration

Successive approximation analog-to-digital converter (SAR-ADC) are widely used in intelligent sensing fields due to it’s low power consumption, medium and high precision and such characteristics. Traditional binary SAR ADC have non-ideal factors such as DAC capacitor array mismatch and comparator offset, which severely limit it’s performance. Therefore, a self-calibration method for non-ideal factors is proposed in this work, and theoretical derivation and simulation analysis are carried out. A 12-bit non-binary SAR ADC with self-calibration is designed based on the TSMC 40nm CMOS process, which reduces the capacitance area, improves the conversion accuracy, and eliminates most of the errors caused by non-ideal factors. Simulation results show that the ADC’s SNDR is 72.01dB, and INL within +1.2/-1LSB, meets most of the market requirements.

HKROC: an integrated front-end ASIC to readout photomultiplier tubes for the Hyper-Kamiokande experiment

The HKROC ASIC was originally designed to readout the photomultiplier tubes (PMTs) for the Hyper-Kamiokande (HK) experiment. HKROC is a very innovative ASIC capable of readout a large number of channels satisfying stringent requirements in terms of noise, speed and dynamic range. Each HKROC channel features a low-noise preamplifier and shapers, a 10-bit successive approximation Analog-to-Digital Converter (SAR-ADC) (designed by AGH Krakow) for the charge measurement (up to 2500 pC) and a Time-to-Digital Converter (TDC) (designed by CEA IRFU group) for the Time-of-Arrival (ToA) measurement with 25 ps binning. HKROC is auto-triggered and includes all necessary ancillary services as bandgap circuit, PLL (Phase-locked loop) and threshold DACs (Digital to Analog Converters). This paper will describe the ASIC architecture and the experimental results of the first HKROC prototype received in January 2022.

A Novel 12-Bit 0.6-mW Two-Step Coarse-Fine Time-to-Digital Converter

A novel two-step coarse-fine time-to-digital converter (TDC) is fabricated in 65-nm CMOS, with a relaxation oscillator based peak counter (ROC) for the coarse stage and a successive approximation analog-to-digital converter (SAR-ADC) for the fine stage. A reconfigurable 3-bit digital counter expands the dynamic range, and a high-precision 9-bit SAR-ADC ensures the resolution. The proposed ROC-ADC scheme conducts the time residence and the transfer linearity well for two-step quantization. Experimental results show that the presented 12-bit TDC achieves a high resolution less than 8 ps and a wide dynamic range up to 30 ns, with the differential nonlinearity (DNL) and integral nonlinearity (INL) values of 0.92 LSB and 1.07 LSB, respectively. The TDC consumes a low power of 0.6 mW from a 1-V supply, with the active area of 0.14 mm2.

Versatile DAC-less successive approximation ADC architecture for medium speed data acquisition

Implementation of the DAC is usually the bottleneck in designing a SAR ADC. Here an innovative DAC-less SAR (DLSAR) ADC architecture is presented which alleviates some drawbacks of the conventional SAR counterpart. The proposed DLSAR binary search algorithm is comprised of two arithmetic operations of division-by-two and subtraction to emulate the DAC function. The hardware of the DLSAR ADC is implemented using ordinary circuit building blocks of a SAR ADC but with less complexity and more robustness against PVT variations as DAC is removed. The developed DLSAR architecture is versatile so that the converter hardware could be readily reconfigured for different sampling rates and resolutions. Based on post-layout simulations in 0.18 μm CMOS process, the designed 8-bit DLSAR ADC consumes 150 μW of power at 2 MS/s including the asynchronous control logic circuit. The SFDR of the converter is up to 62 dB and the ENOB reaches 7.8 bits while it remains above 7.5 bits across most PVT corners without calibration. Also, by reconfiguring the DLSAR ADC to 9-bit resolution at 1 MS/s, the ENOB is generally around 8.2 bits achieving a scaled figure-of-merit (SFoM) better than 3.0 Ç/c-s.

NEW METHOD OF ON-LINE SUCCESSIVE-APPROXIMATION ADC CALIBRATION

A new method of successive approximation ADC calibration without interruption of the main conversion process is proposed. The method is based on the use of information redundancy in the form of redundant positional number systems. The method is based on the selection and analysis of unused combinations in the redundant ADC conversion characteristic.

A 70-MS/s Vcm-free 10-bit-resolution SAR ADC with a novel DAC structure to reduce area andparasitic capacitance effect

A 10-bit-resolution successive approximation ADC with 70-Ms/s conversion rate and with a new configuration for capacitive DAC is represented in this paper. In the DAC structure proposed in this paper, the capacitors that form the Sub-DAC are smaller than the capacitors of the Sub-DAC of the other structures; therefore, the occupied area and the average switching energy in the proposed structure are less than in the other split-array structures, and the proposed structure is less susceptible to parasitic capacitance. Compared to the conventional split-array structure, the total capacitance and Sub-DAC parasitic capacitance are reduced by 15.87% and 46.87%, respectively. Also, the coupling capacitor is a unit capacitor, which improves the capacitor matching in the DAC array furthermore.To design and simulate the proposed 10-bit converter, 180-nm CMOS technology is used. Results of simulation prove that at 70 MS/s operating frequency, with a power supply equal to 1.8 V, and at Nyquist input frequency, SNDR of the proposed converter is 58.26 dB, that means ENOB is 9.39 bit, and SFDR is 64.87 dB. Consequently, the ADC FOM is equal to 123.5 fJ/conversion-step. Also, ramp-test simulation proves that INL and DNL are 0.53/+0.63 LSB and −0.6/+0.6 LSB, respectively. The proposed design consumes 5.8 mw at 70 MS/s operating frequency.

RETRACTED ARTICLE: A 9-bit pseudo-noise-based calibrated successive approximation ADC with differential/integral nonlinearity enhancement

RETRACTED ARTICLE: A 9-bit pseudo-noise-based calibrated successive approximation ADC with differential/integral nonlinearity enhancement

HGCROC3: the front-end readout ASIC for the CMS High Granularity Calorimeter

For the CMS High Granularity Calorimeter (CE), the final version of the 72-channel front-end ASIC (HGCROC3) was submitted in December 2020. HGCROC3 includes low-noise/high-gain preamplifiers/shapers and a 10-bit 40 MHz successive approximation ADC (SAR-ADC) that provide the charge measurement over the linear range of the preamplifier. In the saturation range, a discriminator and a time-to-digital converter (TDC) provide the charge information from the time over threshold (ToT; 200 ns dynamic range, 50 ps binning). A fast discriminator and another TDC provide timing information to 25 ps accuracy. The chip embeds all necessary ancillary services: bandgap circuit, PLL, threshold DACs. We present the experimental results on the latest and final version (HGCROC3) received in April 2021.

An Area-Efficient SAR ADC With Mismatch Error Shaping Technique Achieving 102-dB SFDR 90.2-dB SNDR Over 20-kHz Bandwidth

To minimize the area of analog-to-digital converters (ADCs) for multichannel applications and break the SNDR limitation caused by DAC-induced nonlinearity, a more area-efficient mismatch error shaping (MES) scheme is proposed in noise shaping (NS) successive-approximation (SAR) ADC. By employing a switched-capacitor (SC) voltage divider, the proposed method makes the flash ADC and data weighted averaging (DWA) digital circuits in the original MES method obsolete. Therefore, the complexity of the architecture is highly reduced, and the area is significantly reduced to 0.037 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . In addition, the power consumption for the MES implementation is significantly decreased by more than 7.3%. The proposed SAR ADC is fabricated in GF 40-nm CMOS technology. The measurements show that the proposed MES technique improves the SFDR from 64 to 102 dB and decreases the THD from -63.6 to -95.7 dB. The SNR and SNDR in a 20-kHz bandwidth are 91.6 and 90.2 dB, respectively. The power consumption is 383.4 μW with a 1.1-V power supply at a 16-MS/s sampling rate.

Implementation of 32-BIT Pipelined ADC Using 90nm Analog CMOS Technology

After seeing the technological evolution, we have understood about the A/D converter that it is the meeting point of the analog to digital domains. As technology is being continuously scaled down, the transistor sizes have decreased drastically resulting in reduced area and power consumption in the digital domain. The successive approximation ADC is best suitable for low power applications with moderate speed and simple design. Here, the implementation of 32-bit pipelined analog-to-digital converter with the help of successive approximation register based Sub-ADC. The SAR ADC architectures are popular for achieving high energy efficiency and low power applications. But they suffer from resolution and speed limitation. To overcome the speed limitations of SAR ADC, we proposed the implementation of 90nm using CMOS technology of a low power, high speed pipelined analog-to-digital converter (ADC). The capacitive digital-to-analog converter (DAC), two stage CMOS comparator with output inverter of proposed ADC are lower than those of a conventional ADC. To achieve low power and to minimize the size of the input sampling capacitance in order to ease durability.

MF-Net: Compute-In-Memory SRAM for Multibit Precision Inference Using Memory-Immersed Data Conversion and Multiplication-Free Operators

We propose a co-design approach for compute-in-memory inference for deep neural networks (DNN). We use multiplication-free function approximators based on l <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sub> norm along with a co-adapted processing array and compute flow. Using the approach, we overcame many deficiencies in the current art of in-SRAM DNN processing such as the need for digital-to-analog converters (DACs) at each operating SRAM row/column, the need for high precision analog-to-digital converters (ADCs), limited support for multi-bit precision weights, and limited vector-scale parallelism. Our co-adapted implementation seamlessly extends to multi-bit precision weights, it doesn't require DACs, and it easily extends to higher vector-scale parallelism. We also propose an SRAM-immersed successive approximation ADC (SA-ADC), where we exploit the parasitic capacitance of bit lines of SRAM array as a capacitive DAC. Since the dominant area overhead in SA-ADC comes due to its capacitive DAC, by exploiting the intrinsic parasitic of SRAM array, our approach allows low area implementation of within-SRAM SA-ADC. Our 8×62 SRAM macro, which requires a 5-bit ADC, achieves ~105 tera operations per second per Watt (TOPS/W) with 8-bit input/weight processing at 45 nm CMOS. Our 8×30 SRAM macro, which requires a 4-bit ADC, achieves ~84 TOPS/W. SRAM macros that require lower ADC precision are more tolerant of process variability, however, have lower TOPS/W as well. We evaluated the accuracy and performance of our proposed network for MNIST, CIFAR10, and CIFAR100 datasets. We chose a network configuration which adaptively mixes multiplication-free and regular operators. The network configurations utilize the multiplication-free operator for more than 85% operations from the total. The selected configurations are 98.6% accurate for MNIST, 90.2% for CIFAR10, and 66.9% for CIFAR100. Since most of the operations in the considered configurations are based on proposed SRAM macros, our compute-in-memory's efficiency benefits broadly translate to the system-level.

BIT ERROR NOTIFICATION AND ESTIMATION IN REDUNDANT SUCCESSIVE-APPROXIMATION ADC

The article is devoted to research on the possibilities to use redundant number systems for bit error notification in a successive-approximation ADC during the main conversion mode. The transfer function of a successive-approximation ADC with a non-binary radix is analyzed. If the radix is less than 2, not all possible code combinations appear on the converter output. The process of formation of unused combinations is investigated. The relationship between the bit’s deviations and the list of unused combinations is established. The possibilities of estimating the bit error value without interrupting the process of analog-to-digital conversion is considered.