A 70-MS/s Vcm-free 10-bit-resolution SAR ADC with a novel DAC structure to reduce area andparasitic capacitance effect

Abstract

A 10-bit-resolution successive approximation ADC with 70-Ms/s conversion rate and with a new configuration for capacitive DAC is represented in this paper. In the DAC structure proposed in this paper, the capacitors that form the Sub-DAC are smaller than the capacitors of the Sub-DAC of the other structures; therefore, the occupied area and the average switching energy in the proposed structure are less than in the other split-array structures, and the proposed structure is less susceptible to parasitic capacitance. Compared to the conventional split-array structure, the total capacitance and Sub-DAC parasitic capacitance are reduced by 15.87% and 46.87%, respectively. Also, the coupling capacitor is a unit capacitor, which improves the capacitor matching in the DAC array furthermore.To design and simulate the proposed 10-bit converter, 180-nm CMOS technology is used. Results of simulation prove that at 70 MS/s operating frequency, with a power supply equal to 1.8 V, and at Nyquist input frequency, SNDR of the proposed converter is 58.26 dB, that means ENOB is 9.39 bit, and SFDR is 64.87 dB. Consequently, the ADC FOM is equal to 123.5 fJ/conversion-step. Also, ramp-test simulation proves that INL and DNL are 0.53/+0.63 LSB and −0.6/+0.6 LSB, respectively. The proposed design consumes 5.8 mw at 70 MS/s operating frequency.