Successive Approximation ADC Research Articles

Segmented Architecture for Successive Approximation Analog-to-Digital Converters

In this paper, the structure of a binary-weighted capacitive digital-to-analog converter (DAC) in a successive-approximation analog-to-digital converter (SA-ADC) is modified to a unary or segmented configuration to reduce the power consumption and improve the static linearity performance. In order to be able to choose the optimum value of the segmentation degree (i.e., the number of unary bits), the power consumption and the static linearity behavior of the segmented architecture as functions of the segmentation degree are analyzed. Circuit-level simulation results are presented to show the accuracy of the proposed equations. It is shown that for moderate and high-resolution ADCs, a segmentation degree of four or five bits is the optimum choice from the power-consumption viewpoint. Simulation results of a 1 V, 10-bit, 100-kS/s SA-ADC show that the power consumption of the entire capacitive DAC and the digital circuit of the segmented implementation with a segmentation degree of 4 is 30% less than the conventional design while the standard deviation of the differential nonlinearity is reduced by a factor of 2√(2).

A Switch-Capacitor DAC Successive Approximation ADC Using Regulated Clocked Current Mirror

This paper presents a novel design of switch capacitor DAC successive approximation analog to digital converter (SAR-ADC) using regulated clocked current mirrors. The regulated clocked current mirror (RCCM) design is introduced to source (and sink) the constant current to (and from) the only capacitor in the circuit. The RCCM functions dynamically providing invariable current when required. Moreover when active, RCCM is capable of stabilizing the output current even in presence of voltage variations at its output. DC reference current from RCCM, charging or discharging the single capacitor in the circuit, is controlled by pulse width modulated signal to realize switch-capacitor DAC. Verilog-A script is written for switch control scheme to generate the control signals for RCCM. A dynamic latched comparator is employed to reduce the power consumption in circuit. An 8-bit SAR ADC that exhibits a maximum sampling frequency of 100 kHz is designed in 90 nm CMOS technology and its working is verified through circuit level simulations. This ADC achieves signal to noise and distortion ratio (SNDR) of 45.62 dB which corresponds to effective number of bits (ENOB) of 7.3 bits. At 1 V supply and 100 kS/s, power consumption in ADC is 6 μW while the calculated peak values of DNL and INL are +1.06/-0.40 LSB and +0.53/-1.33 LSB respectively. 

Development of Self-Calibrating A\/D Converters

Until well after I thought of the self-calibration idea, I believed I was the first one to have recognized the property of the binary weighted capacitor array and exploited it to measure capacitor mismatch - nothing remotely similar had turned up in any of the circuit-type journal or conference publications. I discovered later, to my dismay, McCreary had thought of the same principle and had applied it to characterize capacitor mismatch characteristics [9]. This had been published in IEEE Transactions on Instrumentation and Measurements in 1979 - a journal I had not thought was relevant to data converters. Of course, McCreary used the principle for capacitor matching characterization, not for calibrating ADC's, but he recognized the important symmetry in a binary weighted capacitor array and used it to measure capacitor mismatch. Along with his pioneering work in charge-redistribution ADC's, his work laid the foundation for the self-calibrating ADC work presented here. The self-calibrating ADC improved its own accuracy without a factory calibration or a golden standard for the first time. Many other calibration methods followed for various different types of ADC's including successive-approximation, pipeline, and delta-sigma ADC's, ultimately finding applications in other analog circuits in the form of now popular digitally-assisted analog circuits.

Power Efficient Successive Approximation Registers

In recent years, there has been a growing need for Successive Approximation Register (SAR) Analogto-Digital Converter in medical application such as pacemaker. The demand for long battery life-time in these applications poses the requirement for designing ultra-low power SAR ADCs. The project involves custom design and implementation of 8 bit successive approximation ADC for low power and low frequency signals. The ADC would comprise of a SAR Logic, DAC, a comparator and a sample and hold circuit. The DAC would be designed to reduce the systematic and the symmetric errors using the hierarchical symmetrical switching. The main motivation is to implement design of capacitor array DAC and achieve high speed with medium resolution using 60nm technology. The advantage is matching of capacitor can be achieved better then resistor. The market and cost analysis says current SAR ADC has better future. Here we are using spice backend design Tool.

Adaptive successive approximation ADC for biomedical acquisition system

This work proposes a low-power adaptive successive approximation ADC that operates in 12-bit and 8-bit resolution for data acquisition in biomedical system. A fully differential architecture and an energy-efficient switching scheme are employed. The modified switching operation allows the output voltage of the DAC capacitor array to approach the common mode voltage in order to reduce the offset voltage variation of the comparator. A test chip is implemented using a 0.18-µm CMOS process. The core area is 904×650μm2 The measurement results show that performance integrity and power efficiency are both significantly achieved in 12-bit resolution only. After the test using 1.8-V supply voltage, the SNDR is 65.59dB and ENOB is 10.62 bits. Using 200kS/s sampling rate, the ADC core consumption is 40.24μW and 18.63μW, for 12-bit and 8-bit case, respectively.

A 1V 2.52-kS/s 367nW Rail-to-Rail 10-Bit Successive Approximation ADC

A 10-bit successive approximation (SAR) analog-to-digital converter (ADC) in 90nm CMOS dedicated for sample rate limited applications is presented. The SAR ADC achieves an extra low energy by applying only one pre-opamp and without any low voltage techs in preserving the desired low power. HSPICE simulation results show that at a supply voltage of 1V and an output rate of 2.52kS/s, the SAR ADC performs a peak signal-to-noise-and-distortion ratio of 56.8dB. Our SAR ADC consumes 367nW in the simulation, corresponding to a figure of merits of 258.1fJ/conversion-step. And at lowest sample rate mode with an output rate of 126S/s, the ADC consumes only 21nW.

Low-Power Successive Approximation ADC with 0.5 V Supply for Medical Implantable Devices

Low-Power Successive Approximation ADC with 0.5 V Supply for Medical Implantable Devices

IEEE AESS 2012 Pioneer Award: Evolution of aerospace systems through advancements in electronic miniaturization and digital signal processing technologies

The digital revolution of the late 1960s started to define architectures of next-generation aerospace systems. While extremely modest by today's standards, the advent of semiconductor memories, high speed and resolution analog-to-digital converters (ADCs), and microprocessors offered capabilities that were not possible to realize with analog systems alone. This coupled with electronic miniaturization and digital signal processing (DSP) techniques allowed systems to be smaller, smarter, and more reliable. Upon graduation from UCLA with my undergraduate and graduate degrees in electrical sciences and engineering, I enthusiastically sought employment where I could use my education to advance my field in a significant way. While a graduate student, I taught electronics, electrical engineering, and control systems at Pacific States University, a private college in Los Angeles. My first real-world experience was derived by my employment at Pertec Corporation (Chatsworth, California) as an engineer in the development of computer peripherals that included tape transports, disc drives, and formatters. I extensively utilized the knowledge I had acquired in the classroom in the design of these systems; however, the most important education I received was the importance of designing systems for performance, quality, and price. While the job offered me numerous opportunities and I worked with an excellent team, I was hoping for more creative challenges. The opportunity arrived in 1975 when Systron Donner Corporation's Microwave Division (SDMD) offered me a position as a project engineer to develop the company's first spectrum analyzer with digital storage display. SDMD was one of three leading companies specializing in radio frequency (RF) and microwave components and instrumentation. The company's line of spectrum analyzers used the bulky, expensive analog storage tubes, which had severe limitations, including display flicker, poor reliability, and the inability to view multiple waveforms simultaneously. I was promised a technician, a junior engineer, and an assembler who would be devoted solely to my project. Gullible as I was in those days, I believed in this support that I was going to receive only to realize shortly thereafter that due to "emergencies on other projects," I would be the lone warrior championing this project. In hindsight, I believe that this was the greatest learning experience of my life. Not only did I design the entire system, but I learned the value of proper soldering, circuit layout, interface between analog and digital circuits, and noise reduction techniques. The digital storage spectrum analyzer incorporated an 8-bit successive approximation ADC and eight of Intel's newly introduced 2101 (1K×1) random access memories to create a memory with 256×1024 resolution. This, together with DSP techniques, proved capable of processing the downconverted intermediate frequency from the RF/microwave tracking receiver to replace the bulky, expensive, and inefficient analog storage tube-based analyzer and provided, never before realized features, such as adaptive sweep, electronic frequency marker, electronic baseline clipper, simultaneous viewing of multiple waveforms, and other important features [1]. For its time, this contribution was considered seminal and resulted in three important patents for SD, with me as the sole inventor [2], [3], [4].

4-비트 축차근사형 아날로그-디지털 변환기를 내장한 2.5V 0.25㎛ CMOS 온도 센서

본 논문에서는 칩 내부의 온도를 측정하기 위한 CMOS 온도 센서가 제안된다. 제안하는 온도 센서는 칩 내부의 온도에 비례하는 전압을 생성하는 proportional-to-absolute-temperature (PTAT) 회로와 디지털 인터페이스를 위한 4-비트 아날로그-디지털 변환기로 구성된다. 소면적을 가지는 PTAT 회로는 CMOS 공정에서 vertical PNP 구조를 이용하여 설계된다. 온도변화에 둔감한 저전력 4-비트 아날로그-디지털 변환기를 구현하기 위해 아날로그 회로를 최소로 사용하는 축차근사형 아날로그-디지털 변환기가 이용되며, 이를 위해 커패시터-기반 디지털-아날로그 변환기와 시간-도메인 비교기를 이용한다. 제안된 온도 센서는 2.5V <TEX>$0.25{\mu}m$</TEX> 1-poly 6-metal CMOS 공정에서 제작되었고, <TEX>$50{\sim}150^{\circ}C$</TEX> 온도 범위에서 동작한다. 구현된 온도 센서의 면적과 전력 소모는 각각 <TEX>$130{\times}390{\mu}m^2$</TEX>과 <TEX>$868{\mu}W$</TEX>이다. In this paper, a CMOS temperature sensor is proposed to measure the internal temperature of a chip. The temperature sensor consists of a proportional-to-absolute-temperature (PTAT) circuit for a temperature sensing part and a 4-bit analog-to-digital converter (ADC) for a digital interface. The PTAT circuit with the compact area is designed by using a vertical PNP architecture in the CMOS process. To reduce sensitivity of temperature variation in the digital interface circuit of the proposed temperature sensor, a 4-bit successive approximation (SA) ADC using the minimum analog circuits is used. It uses a capacitor-based digital-to-analog converter and a time-domain comparator to minimize power consumption. The proposed temperature sensor was fabricated by using a <TEX>$0.25{\mu}m$</TEX> 1-poly 6-metal CMOS process with a 2.5V supply, and its operating temperature range is from 50 to <TEX>$150^{\circ}C$</TEX>. The area and power consumption of the fabricated temperature sensor are <TEX>$130{\times}390{\mu}m^2$</TEX> and <TEX>$868{\mu}W$</TEX>, respectively.

A new non-uniform adaptive-sampling successive approximation ADC for biomedical sparse signals

This paper presents a new sampling technique and a successive approximation analog to digital converter (SA-ADC) which samples sparse signals in a non-uniform adaptive way. The proposed sampling te...

A 72-dB-SNDR rail-to-rail successive approximation ADC using mismatch calibration techniques

When the voltage of an analog input signal is equal to the supply voltage, it is difficult for a conventional successive approximation ADC to correctly convert the analog signal into digital signal. This paper introduces an improved successive approximation ADC, which can convert the rail-to-rail input range and reduce sampling time through a track-and-hold circuit. Comparator offset cancellation and capacitor self-calibration techniques are used in this ADC. Measurement results show that the peak SNDR of this ADC reaches 72 dB and the signal effective bandwidth is up to 1.25 MHz. It consumes 1 mW in the test, and the figure of merit is 123 fJ/conversion-step.

A 90-MS/s 11-MHz-Bandwidth 62-dB SNDR Noise-Shaping SAR ADC

Although charge-redistribution successive approximation (SAR) ADCs are highly efficient, comparator noise and other effects limit the most efficient operation to below 10-b ENOB. This work introduces an oversampling, noise-shaping SAR ADC architecture that achieves 10-b ENOB with an 8-b SAR DAC array. A noise-shaping scheme shapes both comparator noise and quantization noise, thereby decoupling comparator noise from ADC performance. The loop filter is comprised of a cascade of a two-tap charge-domain FIR filter and an integrator to achieve good noise shaping even with a low-quality integrator. The prototype ADC is fabricated in 65-nm CMOS and occupies a core area of 0.03 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Operating at 90 MS/s, it consumes 806 μW from a 1.2-V supply.

A Single-Channel, 1.25-GS/s, 6-bit, 6.08-mW Asynchronous Successive-Approximation ADC With Improved Feedback Delay in 40-nm CMOS

A single-channel, asynchronous successive-approximation (SA) ADC with improved feedback delay is fabricated in 40 nm CMOS. Compared with a conventional SAR structure that employs a single quantizer controlled by a digital feedback logic loop, the proposed SAR-ADC employs multiple quantizers for each conversion bit, clocked by an asynchronous ripple clock that is generated after each quantization. Hence, the sampling rate of the 6-bit ADC is limited only by the six delays of the Capacitive-DAC settling and each comparator's quantization delay, as the digital logic delay is eliminated. Measurement results of the 40 nm-CMOS SAR-ADC achieves a peak SNDR of 32.9 dB and 30.5 dB, at 1 GS/s and 1.25 GS/s, consuming 5.28 mW and 6.08 mW, leading to a FoM of 148 fJ/conv-step and 178 fJ/conv-step, respectively, in a core area less than 170 um by 85 um.

Statistical Analysis of ENOB and Yield in Binary Weighted ADCs and DACS With Random Element Mismatch

Mismatch motivates many of the design decisions for binary weighted, ratiometric converters, such as successive approximation (SAR) analog-to-digital converters (ADC), but the statistical relationship between mismatch and signal-to-noise-plus-distortion ratio (SNDR) has not been precisely quantified. In this paper, we analyze the effects of capacitor mismatch in a binary weighted, charge redistribution SAR ADC and derive a new analytic expression relating capacitor mismatch and the effective-number-of-bits (ENOB). We then explore the statistics of this new expression and develop a model that accurately predicts yield in terms of ENOB. Finally, the major results of this paper are generalized into a simple and compact design equation that relates resolution, mismatch, and ENOB to yield for all binary weighted, ratiometric converters. The expressions derived in this paper offer practical insight into the relationship between mismatch and performance for all binary, weighted ratiometric converters with these results validated through numerical simulations.

마이크로 전력의 축차근사형 아날로그-디지털 변환기를 위한 시간 도메인 비교기

본 논문에서는 저전압 고해상도 축차근사형 아날로그-디지털 변환기를 위한 시간-도메인 비교기를 제안한다. 제안하는 시간-도메인 비교기는 클럭 피드-스루 보상회로를 포함한 전압제어지연 변환기, 시간 증폭기, 그리고 바이너리 위상 검출기로 구성된다. 제안하는 시간-도메인 비교기는 작은 입력 부하 캐패시턴스를 가지며, 클럭 피드-스루 노이즈를 보상한다. 시간-도메인 비교기의 특성을 분석하기 위해 다른 시간-도메인 비교기를 가지는 두 개의 1V 10-bit 200-kS/s 축차근사형 아날로그-디지털 변환기가 0.18-<TEX>${\mu}m$</TEX> 1-poly 6-metal CMOS 공정에서 구현된다. 11.1kHz의 아날로그 입력신호에 대해 측정된 SNDR은 56.27 dB이며, 제안된 시간-도메인 비교기의 클럭 피드-스루 보상회로와 시간 증폭기가 약 6 dB의 SNDR을 향상시킨다. 구현된 10-bit 200-kS/s 축차근사형 아날로그-디지털 변환기의 전력소모와 면적은 각각 10.39 <TEX>${\mu}W$</TEX>와 0.126 mm2 이다. In this paper, a time-domain comparator is proposed for a successive approximation (SA) analog-to-digital converter (ADC) with a low power and high resolution. The proposed time-domain comparator consists of a voltage-controlled delay converter with a clock feed-through compensation circuit, a time amplifier, and binary phase detector. It has a small input capacitance and compensates the clock feed-through noise. To analyze the performance of the proposed time-domain comparator, two 1V 10-bit 200-kS/s SA ADCs with a different time-domain comparator are implemented by using 0.18-<TEX>${\mu}m$</TEX> 1-poly 6-metal CMOS process. The measured SNDR of the implemented SA ADC is 56.27 dB for the analog input signal of 11.1 kHz, and the clock feed-through compensation circuit and time amplifier of the proposed time-domain comparator enhance the SNDR of about 6 dB. The power consumption and area of the implemented SA ADC are 10.39 <TEX>${\mu}W$</TEX> and 0.126 mm2, respectively.

A 1.92-Megapixel CMOS Image Sensor With Column-Parallel Low-Power and Area-Efficient SA-ADCs

This paper presents a CMOS image sensor with 10-bit column-parallel successive approximation analog-to-digital converters (SA-ADCs). The SA-ADC in each column integrates the binary-weighted references instead of using an internal digital-to-analog converter (DAC) to reduce the area. The area of the column 10-bit SA-ADC is 9 μm × 425 μm. The area of the capacitor array in the SA-ADC is reduced to only 2.8% compared with that of a conventional binary-weighted capacitor DAC. In order to reduce the power consumption, the SA-ADC uses the switched power technique. The constant analog-to-digital conversion time and the switched power technique increase the power saving rate as the frame rate decreases. The proposed image sensor has been fabricated using a 0.13-μm CMOS process. The measured power consumption of the proposed SA-ADC is reduced to 85% and 58% of that in the SA-ADC without the switched power technique at the frame frequencies of 15 and 150 frames/s, respectively.

Smart Car Design and Implement Based on SCM AT89C55 Application

A microcontroller AT89C55 was used as the detection and control core of the electric car passing seesaw in the design. Reflective photoelectric switch LTH1550 -01 constitute the patrol line module to guide the car driving; High - performance magnetic sensitive precision small-angle tilt sensor WQH36 -45 was used to detect the state of equilibrium of the electric car; Bridge driver L298 was used to control reversing/forwarding rotation and PWM motor speed control; 12 - bit switched capacitor successive approximation ADC TLC2543 was used to sample electric car’s sensor signal; keyboard and LED display composed of I2C interface keyboard and LED driver ZLG7290 achieve the human-machine interface; voice playback was compose of the single-chip voice chip ISD2590 and small power amplifier LM386. Based on the above complete and reliable hardware circuit design , the use of sophisticated software algorithms to achieve the angle offset feedback loop speed control and self - correction , the exact line inspection guide , making the electric car in various stages can be accurately controlled .

Optimizing the Number of Bits/Stage in 10-Bit, 50Ms/Sec Pipelined A/D Converter Considering Area, Speed, Power and Linearity

Pipeline ADCs are becoming popular at high speeds and with high resolution. This paper discusses the options of number of bits/stage conversion techniques in pipelined ADCs and their effect on Area, Speed, Power Dissipation and Linearity. The basic building blocks like op-amp, Sample and Hold Circuit, sub converter, DAC, Residue Amplifier used in every stage is assumed to be identical. The sub converters use flash architectures. The design is implemented using 0.18�� m CMOS technology and uses 3.3V power supply. The paper implements a 10 bit 50MSPS pipelined ADC using 1, 1.5, 2, 3, 4 and 5 bits/stage conversion and compares them with respect to Area, Speed. Power and Linearity. The paper concludes by stating that 2bits/stage is optimum for a pipelined ADC and to reduce design complexity we can go up to 3 bits/stage. HE rapidly growing electronics has resulted in digital revolution with telephony switching systems in 1970's and continued with digital audio in 1980's and digital video in 1990's. This is expected to prevail in the present multimedia era and even can influence in future systems. Since all electrical signals in nature are analog and since most signal processing is done in the digital domain therefore, A/D and D/A converters have become a necessity. Successive approximation ADC makes single bit decision at a time while flash ADC makes all bit decisions in a single go. Successive approximation ADC is slow and occupies less area while flash ADCs are faster but area increases exponentially with bit length.

A Low Power, 8-Bit, 5MS/s Digital to Analog Converter for Successive Approximation ADC

In this paper, a simple switched capacitor Digital to Analog Converter (DAC) is presented that exhibits monotonicity and occupies small area. The proposed DAC starts its conversion from the MSB instead of the traditional approach of starting from LSB making it suitable for use in cyclic or successive approximation analog-to-digital converters. The reference voltage is sampled once and appropriate charge is transferred to the output capacitor of the DAC. Some issues relevant to the design and their possible solutions are presented. The DAC is designed for a resolution of 8-bit. Sampling speed is chosen to be 5MS/s and the main emphasis is on low power. This DAC consumes power in the order of microwatt (����), compare with previous DACs which consumes more power, generally in the order of milliwatts. The output 8-bits along with power dissipation of 493.8 �� W has been achieved. Index Terms—DAC, Folded Cascode, SAR ADC, Transmission gates.

High Resolution Successive Approximation ADC for Low Power Biomedical Applications

High Resolution Successive Approximation ADC for Low Power Biomedical Applications