Substrate Hot Electron Injection Research Articles

The promising multi-bit/level programming operations for nano-scaled SONOS memory

In order to obtain a reliable multi-bit/level operation for nano-scaled polycrystalline silicon-oxide-nitride-oxide-silicon (SONOS) memory, two different localized charge-injection programming methods, the channel hot electron injection with a positive substrate bias (CHEI-P) and pulse agitated substrate hot electron injection (PASHEI), are operated in 90nm SONOS cells. It is found that the cells programmed by CHEI-P have the better endurance property than by PASHEI. The better endurance is due to the less accumulation of charges in the nitride layer, evidenced by surface potential profiling technique. CHEI-P program further exhibits the superior endurance and retention properties after 104 program/erase cycles in 4-bit/4-level operations. These results illustrate that CHEI-P program is a promising candidate for multi-bit/levels nano-sized SONOS memory.

Pulse-agitated self-convergent programming for 4-bit per cell dual charge storage layer flash memory

A pulse-agitated (PA) self-convergent programming (SCP) scheme is proposed for 4-bit per cell vertically dual charge storage layer (DCSL) Flash memory operation in NOR-circuits. PA substrate hot electron injection (PASHEI) is used for programming, and hot hole injection (HHI) is used for erasing. Localized PASHEI enables separated data nodes, while clear electron energy modulation gives rise to accurate multi-level threshold voltage ( V th) control in the step-up potential wells of the DCSL devices. Excellent 4-bit cell reliability is maintained for the DCSL devices throughout the 10 5 programming/erasing (P/E) cycles, and inter-cell disturbances are suppressed.

Electrical characterization of high-k gate dielectrics on semiconductors

This paper reviews the following electrical characterization techniques for measuring the microscopic bonding structures, impurities, and electrically active defects in advanced CMOS gate stacks: (1) inelastic electron tunneling spectroscopy (IETS), (2) lateral profiling of threshold voltages, interface-trap density, and oxide charge density distributions along the channel of a MOSFET, and (3) pulse agitated substrate hot electron injection (PASHEI) technique for measuring trapping effects in the gate dielectric at low and modest gate voltages.

Novel electrical characterization for advanced CMOS gate dielectrics

This paper reviews the following electrical characterization techniques for measuring the microscopic bonding structures, impurities, and electrically active defects in advanced CMOS gate stacks: 1) inelastic electron tunneling spectroscopy (IETS), 2) lateral profiling of threshold voltages, interface-trap density, and oxide charge density distributions along the channel of an MOSFET, and 3) pulse agitated substrate hot electron injection (PASHEI) technique for measuring trapping effects in the gate dielectric at low and modest gate voltages.

Electron energy dependence of defect generation in high-k gate stacks

In this work, we employ the substrate hot electron injection technique as a characterization tool to examine the defect creation mechanisms in high-k HfSiON gate stacks, taking advantage of the independent control over oxide field, electron fluence, and injected electron energy which the technique allows. We show that defect creation and oxide breakdown are dependent on the energy of the injected electrons and not on the oxide field. Furthermore, we show that the energy of the injected electrons governs whether the majority of the defects are created at the Si∕SiO2 interface or in the bulk of the material. Results show that at operating conditions, the primary threat to device reliability from hot carrier damage is the introduction of a permanent 3D positive bias temperature instability component introduced by increased interface trap generation, even for carriers with energy slightly above that of field accelerated electrons. We also discuss the feasibility of using substrate hot electron injection as a means to accelerate time dependent dielectric breakdown measurements, thereby allowing degradation at lower oxide fields to be probed.

Electrical Characterization of Advanced Gate Dielectrics for Scaled CMOS Technology

This paper reviews the following electrical characterization techniques for measuring the microscopic bonding structures, impurities, and electrically active defects in advanced CMOS gate stacks: (1) Inelastic Electron Tunneling Spectroscopy (IETS), (2) lateral profiling of threshold voltages, interface-trap density, and oxide charge density distributions along the channel of a MOSFET, and (3) PASHEI (Pulse Agitated Substrate Hot Electron Injection) technique for measuring trapping effects in the gate dielectric at low and modest gate voltages.

Charge pumping spectroscopy: HfSiON defect study after substrate hot electron injection

Spectroscopic charge pumping (CP) is used to study the evolution of the energy distribution of trapped electrons within HfSiON/SiO 2 gate stacks under substrate hot electron injection (SHEI). Base level CP measurements with large pulse amplitude allow an efficient charging/discharging of traps and reaching two defect bands in the HfSiON situated at 0.40 and 0.85 eV above the Si conduction band, respectively. Unlike standard constant voltage stress (CVS), SHEI enables full control of the stress by separately controlling the applied gate field, the injected electron energy, and the fluence. During CVS, HfSiON defects at 0.40 eV are generated. Conversely, during SHEI, either the shallow or the deep defects are preferentially created depending on the gate field as well as electron energy.

Electrical Characterization of Advanced Gate Dielectrics

The following electrical characterization techniques for measuring the microscopic bonding structures, impurities, and electrically active defects associated with advanced gate stacks will be reviewed: (1) Inelastic Electron Tunneling Spectroscopy (IETS), (2) lateral profiling of threshold voltages, interface-trap density, and oxide charge density distributions along the channel of a MOSFET, (3) separation of interface traps from bulk dielectric traps; and (4) PASHEI (Pulse Agitated Substrate Hot Electron Injection) technique for measuring trapping effects in the gate dielectric.

Charge Trapping at Deep States in Hf–Silicate Based High- κ Gate Dielectrics

We have observed charge trapping during constant voltage stress in Hf-based high-κ dielectrics at deep traps as well as at the shallow traps. and leakage current dependence on these deep traps further suggest that trapping at deep levels inhibits fast recovery. The earlier findings where charge trapping seemed to be very transient due to the presence of a large number of shallow traps and trapped charge could be eliminated by applying a reverse direction electric field may no longer be valid. The experimentally observed trap energy levels from low-temperature measurements establish a relationship between the origin of the deep traps and their dependence on O vacancy formation in Hf–silicate-based films. Substrate hot electron injection gives rise to significant electron trapping and slow post-stress recovery under negative bias conditions, which confirms that O-vacancy-induced deep defects determine the transient behavior in Hf–silicate-based high-κ gate dielectrics. It is further shown that negative-U transition to deep defects is responsible for trap-assisted tunneling under substrate injection. A fraction of the injected electrons remains trapped at the deep defects and gives rise to significant . This has the potential to be the ultimate limiting factor for the long-term reliability of Hf-based high-κ gate dielectrics.

Band-to-band tunneling induced substrate hot electron injection (BBISHE) to perform programming for NOR flash memory

A new proposed flash memory with divided p-substrate-line (PBL) in modified NOR-type array is described. The programming method of band-to-band tunneling induced substrate hot electron injection (BBISHE) provides high programming efficiency. Realized in NOR-type array and combining with the channel FN ejection erasure, the cell guarantees fast random access capability. The BBISHE programming flash memory features high programming efficiency, low voltage operation, high-speed and reliability up to 10 4 P/E cycles.

Ultrathin oxide reliability after combined constant voltage stress and substrate hot electron injection

An experimental investigation on ultra-thin oxides under combined substrate hot-electron injection (SHEI) and tunnelling electrical stress (CVS) is reported. We study the electrical properties of 2.5–1.5 nm-thick SiO 2 oxides in N-channel metal–oxide–semiconductor (NMOS) field effect transistors. CVS stress at V G = +3.5 V does not affect the transistor operating parameters but does increase, up to a factor of 10, the gate current. We have verified that the critical parameter of CVS stress is the gate voltage bias, consequently we suggest a model based on energetic electrons creating damage, which, correctly describes the reliability of ultra-thin SiO 2 at CVS condition. In comparison SHEI is observed to be not only dependent on gate bias but also on the electric field in the oxide. A comparison of each parameter either injected charge or current, gate and substrate voltage or oxide field is experimentally done. Based on these and previous results, the defect creation probability for CVS and SHEI stress is fitted over gate voltage to resolve two defect generation mechanisms.

Experimental extraction of degradation parameters after constant voltage stress and substrate hot electron injection on ultrathin oxides

The impact of hot electrons on gate oxide degradation is studied by investigating devices under constant voltage stress and substrate hot electron injection in thin silicon dioxide (2.5–1.5 nm). The build-up defects measured using low voltage stress induced leakage current is reported. Based on these results, we propose to extract the critical parameter of the degradation under simultaneous tunnelling and substrate hot-electron stress. During a constant voltage stress the oxide field, the injected charge and the energy of carriers are imposed by V G and cannot be studied independently. Substrate hot electron injection allows controlling the current density independent of the substrate bias and oxide voltage. The results provide an understanding for describing the reliability and the parameters dependence under combined substrate hot electron injection and constant voltage stress tunnelling.

Investigation of the Energy Distribution of Stress-Induced Oxide Traps by Numerical Analysis of the TAT of HEs

This paper investigates by numerical modeling the results of substrate hot electron (SHE) injection experiments in virgin and stressed devices and the corresponding increase of the contribution of HEs to the gate current due to the stress-induced oxide traps. Experimental evidence of HE trap-assisted tunneling (HE TAT) is found after Fowler-Nordheim (FN) stress and SHE stress. An accurate physically based model developed to interpret the experimental results allowed us to study the energy distribution of generated oxide traps in the two different stress regimes. It is found that degradation in HE stress conditions and FN stress conditions cannot be explained by the same trap distribution. For a given stress-induced low field leakage current, a larger concentration of traps in the top part of the oxide band gap is needed to explain HE TAT after SHE stress than after FN stress. The range of trap energy where each technique is sensitive is also identified.

Enhanced negative substrate bias degradation in nMOSFETs with ultrathin plasma nitrided oxide

The degradation induced by substrate hot electron (SHE) injection in 0.13-/spl mu/m nMOSFETs with ultrathin (/spl sim/2.0 nm) plasma nitrided gate dielectric was studied. Compared to the conventional thermal oxide, the ultrathin nitrided gate dielectric is found to be more vulnerable to SHE stress, resulting in enhanced threshold voltage (V/sub t/) shift and transconductance (G/sub m/) reduction. The severity of the enhanced degradation increases with increasing nitrogen content in gate dielectric with prolonged nitridation time. While the SHE-induced degradation is found to be strongly related to the injected electron energy for both conventional oxide , and plasma-nitrided oxide, dramatic degradation in threshold voltage shift for nitrided oxide is found to occur at a lower substrate bias magnitude (/spl sim/-1 V), compared to thermal oxide (/spl sim/-1.5 V). This enhanced degradation by negative substrate bias in nMOSFETs with plasma-nitrided gate dielectric is attributed to a higher concentration of paramagnetic electron trap precursors introduced during plasma nitridation.

Reliability of ultra-thin silicon dioxide under substrate hot-electron, substrate hot-hole and tunneling stress

Substrate hot-electron and substrate hot-hole injection experiments are used to provide insight into defect generation and breakdown of ultra-thin silicon dioxide under constant voltage tunneling stress. Results from substrate hot-electron injection confirm that energetic electrons are responsible for degradation and breakdown of ultra-thin silicon dioxide under tunneling stress conditions. Substrate hot-hole injection experiments suggest that mechanisms other than trapping of hot holes may be responsible for the breakdown of ultra-thin silicon dioxide.

Electrical reliability aspects of through the gate implanted MOS structures with thin oxides

The effect of through the gate implantation (TGI) on MOS devices with oxide thicknesses of 3.3, 4.0, and 20 nm is studied, utilizing constant voltage stress tests and a substrate hot electron (SHE) injection technique. For 3.3 and 4.0 nm thick oxides, a dependence of time to breakdown on TGI dose is detected which, for 3.3 nm samples, diminishes with increasing test voltage. SHE injection measurements show a TGI induced increase in intrinsic electron trap density and also an increase in trap generation rate during sample stressing. A change of electron trap generation dynamics seems to be the main cause for oxide weakening due to TGI.

A New Dual Floating Gate Flash Cell for Multilevel Operation

A new dual floating gate flash memory cell using constant bias voltages for multilevel operation is proposed to increase memory density. Channel hot electrons (CHE) and drain avalanche hot electrons (DAHE) are used to store different amounts of charge in different floating gates. To erase the data, channel fowler-nordheim (FN) tunneling is applied first, and then substrate hot electron (SHE) injection is utilized to prevent from over erase and tighten the threshold voltage spread. The simulation results indicate that the multilevel flash memory cell with slight modifications of triple well technology is a promising device for future multilevel operation devices.

STUDY ON STRESS INDEUCED LEAKAGE CURRENT TRANSIENT CHARACTERISTICS IN THIN GATE OXIDE

FN tunneling and hot hole (HH) stress induced leakage current (SILC) transient characteristics in thin gate oxide are investigated. Under both stress conditions, the stress induced leakage current obeys a power-law time dependence with different power factor. For HH SILC, the power factor significantly departs from -1. HH SILC is found to have a more pronounced transient effect. The results show that HH SILC can be attributed to positive oxide detrapping and annihilation of positive charge-assisted tunneling current. The latter can be diminished by substrate hot electron injection.

Reliability of ultrathin silicon dioxide under combined substrate hot-electron and constant voltage tunneling stress

An experimental investigation of breakdown and defect generation under combined substrate hot-electron and tunneling electrical stress of silicon oxide ranging in thickness from 2.0 nm to 3.5 nm is reported. Using independent control of the gate current for a given substrate and gate bias, the time-to-breakdown of ultrathin silicon dioxide under substrate hot-electron stress is observed to be inversely proportional to the gate current density. The thickness dependence (2.0 nm to 3.5 nm) of substrate hot-electron reliability is reported and shown to be similar to constant voltage tunneling stress. The build-up of defects measured using stress-induced-leakage-current and charge-pumping for both tunneling and substrate hot-electron stress is reported. Based on these and previous results, a model is proposed to explain the time-to-breakdown behavior of ultrathin oxide under simultaneous tunneling and substrate hot-electron stress. The results and model provide a coherent understanding for describing the reliability of ultrathin SiO/sub 2/ under combined substrate hot-electron injection and constant voltage tunneling stress.

Monte Carlo simulation of hot-electron-induced dielectric breakdown in thin silicon dioxide films

Dielectric breakdown of gate oxide films in MOSFETs is studied by using a substrate hot electron (SHE) injection technique. Monte Carlo simulations are performed to investigate the correlation between the oxide breakdown and the electron energy. It is demonstrated that the holes generated in the anode electrode plays an important role in the oxide degradation induced by SHE injection.