Abstract
The following electrical characterization techniques for measuring the microscopic bonding structures, impurities, and electrically active defects associated with advanced gate stacks will be reviewed: (1) Inelastic Electron Tunneling Spectroscopy (IETS), (2) lateral profiling of threshold voltages, interface-trap density, and oxide charge density distributions along the channel of a MOSFET, (3) separation of interface traps from bulk dielectric traps; and (4) PASHEI (Pulse Agitated Substrate Hot Electron Injection) technique for measuring trapping effects in the gate dielectric.
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