Abstract
The Inelastic Electron Tunneling Spectroscopy (IETS) technique, which relies on tunneling current to probe the ultra-thin gate dielectric in a metal-insulator-semiconductor (MIS) sandwich, is a powerful technique to address materials issues related to reactions and intermixing at interfaces, as well as properties related to carrier mobility and reliability in an advanced CMOS gate stack, such as phonon modes, impurities, and charge traps, for structures that are difficult to accurately characterize by other techniques. The principle of operation, experimental considerations, and examples will be shown in this paper to illustrate the capabilities and limitations of the IETS technique.
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