Abstract
This paper reviews the following electrical characterization techniques for measuring the microscopic bonding structures, impurities, and electrically active defects in advanced CMOS gate stacks: (1) Inelastic Electron Tunneling Spectroscopy (IETS), (2) lateral profiling of threshold voltages, interface-trap density, and oxide charge density distributions along the channel of a MOSFET, and (3) PASHEI (Pulse Agitated Substrate Hot Electron Injection) technique for measuring trapping effects in the gate dielectric at low and modest gate voltages.
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