Submicron Silicon-on-insulator Research Articles

Ultra-High-Q Racetrack Resonators on Thick SOI Platform Through Hydrogen Annealing Smoothing

We implemented a hydrogen annealing based post-processing technique as a tool to improve the sidewall roughness of 3 μm thick silicon-on-insulator (SOI) waveguides and demonstrated ultra-high- <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Q</i> factors on racetrack resonators leveraging on the propagation loss reduction achieved through the smoothing process. The designed racetracks are based on a combination of rib waveguides and strip-waveguide-based Euler bends. We measured intrinsic quality factors of 14×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sup> for a racetrack with a footprint of ∼5.5 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and 10.7×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sup> for a smaller racetrack with footprint of ∼1.48 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The estimated propagation loss for the rib waveguides was ∼2.7 dB/m, representing a ×3 reduction respect to the previously measured losses of 3 μm thick SOI rib waveguides treated with thermal oxidation smoothing. Overall, the post-processing technique allowed to significantly reduce the sidewall roughness without altering the geometry of the waveguides, unlike in sub-micron scale SOI platforms, making it an attractive solution for applications demanding ultra-low losses.

Fabrication-robust silicon photonic devices in standard sub-micron silicon-on-insulator processes.

Perturbations to the effective refractive index from nanometer-scale fabrication variations in waveguide geometry plague high index-contrast photonic platforms; this includes the ubiquitous sub-micron silicon-on-insulator (SOI) process. Such variations are particularly troublesome for phase-sensitive devices, such as interferometers and resonators, which exhibit drastic changes in performance as a result of these fabrication-induced phase errors. In this Letter, we propose and experimentally demonstrate a design methodology for dramatically reducing device sensitivity to silicon width variations. We apply this methodology to a highly phase-sensitive device, the ring-assisted Mach-Zehnder interferometer (RAMZI), and show comparable performance and footprint to state-of-the-art devices, while substantially reducing stochastic phase errors from etch variations. This decrease in sensitivity is directly realized as energy savings by significantly reducing the required corrective thermal tuning power, providing a promising path toward ultra-energy-efficient large-scale silicon photonic circuits.

Modeling of TID-induced leakage current in ultra-deep submicron SOI NMOSFETs

In order to study the total ionizing dose effects (TID)-induced degradation mechanism of 130 ​nm partially depleted (PD) silicon-on-insulator (SOI) NMOSFETs, a SPICE model including the TID effects was established with Verilog-A.The total ionizing dose effects will lead to the threshold-voltage shift and the leakage current increase of SOI NMOSFETs. The increase of leakage current in the STI region is the main factor leading to degradation of characteristics of devices, which will form a parasitic transistor. Based on the standard BSIM SOI process model, the SPICE model of leakage current of the STI parasitic transistor is added, and the variation of equivalent gate width and gate oxide thickness caused by radiation-induced trapped charges are considered.The devices with different width-length-ratios and different bias conditions are considered in our experiments, and the model can effectively reflect the variation of current characteristics before and after radiation, and provide a reference to develop a radiation-hardening technology.

Influence of Self-Heating Effect on I-V Dates of Party Depleted Submicron Silicon-on-Insulator CMOS Transistors at High Ambient Temperatures

To solve the problems of high temperature microelectronics the influence of the self heating effect on the I-V dates partially depleted submicron silicon–on-insulator CMOS transistor in the ambient temperature range from 525 K to 650 K is discussed. Approach consists in combination of experimental data and of computational simulating results. For simulation of electrothermal characteristics of SOI CMOS transistor is considered three-layered structure. Temperature distribution is calculated numerically using iterative algorithm in conjunction with software COMSOL Multiphysics. I-V dates of SOI CMOS transistors are calculated by means of two-dimensional models for n-and p-channel transistors of Sentaurus TCAD developed in the system of instrument and technological modelling. TCAD models are calibrated on experimental characteristics for 525 K. It is shown that with growth of ambient temperature the self-heating mechanism contribution consistently decreases. By results of modeling it is established that self-heating contributions at supply voltages 5.5 V to decreases for n-transistor in 2.8 times, p-transistor in 2.2 times. The relative decline of current n-type transistor for reduced from 11.6% to 5.5% and for p-type with 15% to 9%. However, different dynamics of current recession for n-and p-transistors is significant for analog applications that need to be considered at high-temperature circuit design. The proposed methodology allows to critically assess the contribution of the self-heating mechanism on the I-V dates for a wide range of high temperatures and supply voltages. Underestimating this fact leads to unreasonable values for the maximum temperature and limit of thermal stability for the separate SOI CMOS transistor. In total this can be a prerequisite for a significant simplification of the design of not only the chip construction but also the whole electronic Board.

Quasi-3D TCAD modeling of STI radiation-induced leakage currents in SOI MOSFET structure

Quasi-3D model for calculation of radiation leakage currents in modern submicron Silicon-on-Insulator (SOI) metal–oxide–semiconductor field-effect transistor (MOSFET) structures is proposed. The solution of a complex 3-dimensional problem is reduced to solving two tasks: 2D modeling of the traditional MOSFET cross-section and 3D modeling of the side parasitic transistor. The radiation-induced leakage current simulation in the 0.35 μm SOI MOSFET structure with taking account ionizing radiation with a dose of up to 500 krad was simulated. The results of the simulation show that in comparison with the traditional fully 3D modeling, which requires 11 hours of computer time, the computer time for the IdVg characteristic was reduced to 71 minutes (i.e. the computer time decreased by 9 times).

Impact of X-ray Radiation on SOI MOSFET: Insulator Film Degradation and Hot-Carrier Reliability

This paper discusses the impact of X-ray radiation on the hot-carrier reliability of the silicon-on-insulator (SOI) MOSFET. We examine sub-micron complimentary SOI MOSFETs in order to investigate the various factors influencing device characteristics. Samples on n-channel MOSFETs (fully-depleted inversion-channel devices) and p-channel MOSFETs (accumulation-mode devices) were fabricated using conventional photolithography in the 1990s, and they were subjected to continuous X-ray radiation in the range of 0.1J/cm2 to 5J/cm2 after fabrication. D. c. characteristics of as-irradiated devices and post-annealed devices and hot-carrier reliability of post-annealed devices were fully investigated.

Characterization of pixel sensor designed in 180 nm SOI CMOS technology

A new type of X-ray imaging Monolithic Active Pixel Sensor (MAPS), X-CHIP-02, was developed using a 180 nm deep submicron Silicon On Insulator (SOI) CMOS commercial technology. Two pixel matrices were integrated into the prototype chip, which differ by the pixel pitch of 50 μm and 100 μm. The X-CHIP-02 contains several test structures, which are useful for characterization of individual blocks. The sensitive part of the pixel integrated in the handle wafer is one of the key structures designed for testing. The purpose of this structure is to determine the capacitance of the sensitive part (diode in the MAPS pixel). The measured capacitance is 2.9 fF for 50 μm pixel pitch and 4.8 fF for 100 μm pixel pitch at -100 V (default operational voltage). This structure was used to measure the IV characteristics of the sensitive diode. In this work, we report on a circuit designed for precise determination of sensor capacitance and IV characteristics of both pixel types with respect to X-ray irradiation. The motivation for measurement of the sensor capacitance was its importance for the design of front-end amplifier circuits. The design of pixel elements, as well as circuit simulation and laboratory measurement techniques are described. The experimental results are of great importance for further development of MAPS sensors in this technology.

L-shaped fiber-chip grating couplers with high directionality and low reflectivity fabricated with deep-UV lithography.

Grating couplers enable position-friendly interfacing of silicon chips by optical fibers. The conventional coupler designs call upon comparatively complex architectures to afford efficient light coupling to sub-micron silicon-on-insulator (SOI) waveguides. Conversely, the blazing effect in double-etched gratings provides high coupling efficiency with reduced fabrication intricacy. In this Letter, we demonstrate for the first time, to the best of our knowledge, the realization of an ultra-directional L-shaped grating coupler, seamlessly fabricated by using 193nm deep-ultraviolet (deep-UV) lithography. We also include a subwavelength index engineered waveguide-to-grating transition that provides an eight-fold reduction of the grating reflectivity, down to 1% (-20 dB). A measured coupling efficiency of -2.7 dB (54%) is achieved, with a bandwidth of 62nm. These results open promising prospects for the implementation of efficient, robust, and cost-effective coupling interfaces for sub-micrometric SOI waveguides, as desired for large-volume applications in silicon photonics.

NUMERICAL SIMULATION OF ELECTRIC CHARACTERISTICS OF DEEP SUBMICRON SILICON-ON-INSULATOR MOS TRANSISTOR

Today submicron silicon-on-insulator (SOI) MOSFET structures are widely used in different electronic components and also can be used as sensing elements in some applications. The development of devices based on the structures with specified characteristics is impossible without computer simulation of their electric properties. The latter is not a trivial task since many complicated physical processes and effects must be taken into account. In current study ensemble Monte Carlo simulation of electron and hole transport in deep submicron n-channel SOI MOSFET with 100 nm channel length is performed. The aim of the study is investigation of the influence of interband impact ionization process on the device characteristics and determination of the transistor operation modes when impact ionization process starts to make an appreciable influence on the device functioning. Determination of the modes is very important for adequate and accurate modeling of different devices on the basis of SOI MOSFET structures. Main focus thereby is maid on the comparison of the use of two models of impact ionization process treatment with respect to their influence on the transistor current-voltage characteristics. The first model is based on the frequently used Keldysh approach and the other one utilizes the results obtained via numerical calculations of silicon band structure. It is shown that the use of Keldysh impact ionization model leads to much faster growth of the drain current and provides earlier avalanche breakdown for the SOI MOSFET. It is concluded that the choice between the two considered impact ionization models may be critical for simulation of the device electric characteristics.

Dual-Wavelength Pulse Train Generation Based on Silicon-on-Insulator Optical Waveguides

In this paper, we present and numerically study a method with pump-probe configuration to generate ∼4.17-THz dual-wavelength ultrahigh-repetition-rate pulse train from the continuous-waves (CW) based on the submicron silicon-on-insulator (SOI) optical waveguides. An original ∼4.17 THz repetition rate pulsed pump, with femtosecond pulse duration, at 2900 nm (mid-wave infrared wavelength-MWIR) and 2-channel CW lights at 1450 nm and 1650 nm (near infrared wavelengths) are simultaneously launched into the silicon waveguide. Results show that, when both of CW lights with high intensity pulsed pump are co-propagating along the SOI waveguide, the CW lights will, respectively, experience normal and anomalous group velocity dispersion (GVD) regimes, leading to developing into two inverted ∼4.17 THz repetition rate pulse train by the combined effects of GVD and nonlinear frequency chirp induced by pulsed pump inside the waveguide. Moreover, the outcome pulse trains have short pulse duration and high extinction ratio (ER) comparing with the original pulsed pump if the systems parameters such as input power and waveguide length are judiciously adjusted.

Real-space strain mapping of SOI features using microbeam X-ray diffraction

Synchrotron-based X-ray microbeam measurements were performed on silicon-on-insulator (SOI) features strained by adjacent shallow-trench isolation (STI). Strain engineering in microelectronic technology represents an important aspect of the enhancement in complementary metal-oxide semiconductor device performance. Because of the complexity of the composite geometry associated with microelectronic circuitry, characterization of the strained Si devices at a submicron resolution is necessary to verify the expected strain distributions. The interaction region of the SOI strain extended the SOI film thickness from the STI edge at least 25 times. Regions of 65-nm-thick SOI less than 3 μm wide exhibited an overlap in the strain fields because of the surrounding STI. Microbeam mapping of arrays containing submicron SOI features and embedded STI structures revealed the largest out-of-plane strains because of the close proximity of superimposed strain distributions induced by the STI.

Influence of waveguide geometry on scattering loss effects in submicron strip silicon-on-insulator waveguides

Silicon-on-insulator (SOI) optical waveguides with high electromagnetic field confinement suffer from side-wall roughness, which is responsible for strong scattering inducing propagation loss. A theoretical investigation of the influence of geometry in submicron SOI waveguides on the scattering loss due to side-wall roughness is reported. Scattering loss coefficient is derived for both narrow and flat SOI strip waveguides. It is shown that scattering loss coefficient is significantly increased for narrow waveguides compared with flatter ones. These results show that attention has to be paid to waveguide geometry, as scattering effects are the predominant source of optical losses in strip submicron SOI optical waveguides.

Imaging highly confined modes in sub-micron scale silicon waveguides using Transmission-based Near-field Scanning Optical Microscopy

We demonstrate a new technique for high resolution imaging of near field profiles in highly confining photonic structures. This technique, Transmission-based Near-field Scanning Optical Microscopy (TraNSOM), measures changes in transmission through a waveguide resulting from near field perturbation by a scanning metallic probe. Using this technique we compare different mode polarizations and measure a transverse optical decay length of lambda/15 in sub-micron Silicon On Insulator (SOI) waveguides. These measurements compare well to theoretical results.

Scaling rules for SOI MOSFETs operating in the fully inverted mode

Two-dimensional device simulation was performed on silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect-transistors (MOSFETs) with various gate length L g various top Si layer thickness t Si and various buried oxide (BOX) layer thickness t BOX. As a result, it was found that when t BOX is large, short channel effect (SCE) cannot be suppressed in a fully depleted (FD) MOSFET only by the simple scaling rule maintaining the ratio of L g to top Si layer t Si more than four. It was also found that the scaling rule breaks down more seriously in a fully inverted (FI) MOSFET. It was confirmed that electric field from the drain region penetrates easily into thick BOX layer, which causes drain-induced barrier lowering (DIBL) at the top Si/BOX interface in deep sub-micron gates SOI MOSFETs. Consequently, it was concluded that the DIBL can be suppressed efficiently by reducing t BOX even in a FI MOSFET.

Electron valence-band tunneling-induced Lorentzian noise in deep submicron silicon-on-insulator metal–oxide–semiconductor field-effect transistors

In this article, the impact of several electrical and technological parameters on a particular type of Lorentzian noise, occurring in deep submicron silicon-on-insulator (SOI) metal–oxide–semiconductor field-effect transistors with an ultrathin gate dielectric is described and a semi-empirical model is proposed that captures the main features of the experimental behavior. It is shown that the noise takes place in both n- and p-channel partially depleted SOI transistors. The excess Lorentzians are also found in the n-channel fully depleted devices studied, whereby the noise plateau amplitude [SI(0)] increases for a more negative back-gate bias, putting the back interface into stronger accumulation. The dependence of the characteristic time constant τ and SI(0) on transistor length, drain, front- and back-gate bias is reported, where from a first-order model is derived. The latter is based on the idea that the excess Lorentzian noise originates from filtered shot noise induced by majority carriers, that are injected in the floating body of the transistors by electron valence-band tunneling across the ultrathin (2.5 nm) gate oxide.

The 1/f/sup 1.7/ noise in submicron SOI MOSFETs with 2.5 nm nitrided gate oxide

The low-frequency noise of partially depleted silicon-on-insulator (SOI) MOSFETs is studied in the ohmic regime. In the frequency range 0.7 Hz /spl les/ f /spl les/ 50 Hz, a power spectral density is observed which follows a 1/f/sup n/ law, with n /spl sim/ 1.7 for a broad range of operation conditions. This noise is to be distinguished from the usual 1/f-like noise, occurring at higher frequency for devices with a length smaller than 1 /spl mu/m. From the dependence on the gate voltage and device length, it is concluded that the 1/f/sup 1.7/ noise is of the McWhorter type and, therefore, is generated by carrier exchange between the front channel and traps in the 2.5 nm NO gate oxide. This type of noise is absent in the back-channel or in the gate current. A model will be presented, from which it is derived that the responsible traps are most likely associated with the polysilicon gate/oxide interface and, furthermore, show a steep concentration profile over a small depth range. A similar noise behavior is observed in bulk devices with thin gate dielectrics.

Modeling of drain current overshoot and recombination lifetime extraction in floating-body submicron SOI MOSFETs

This work reports on a new general modeling of recombination-based mechanisms related to electrically floating-body partially-depleted (PD) SOI MOSFETs. The model describes drain current overshoots induced when turning on the transistor gate and suggests a novel extraction method for the recombination lifetime in the silicon film. We show that the recombination process associated with drain current overshoots in PD silicon-on-insulator (SOI) MOSFETs takes place mainly in the depletion region and not in the neutral region as in case of pulsed MOS capacitors. Associated with existing techniques for generation lifetime extraction, our model offers, for the first time, the possibility of complete and rapid characterization for both generation and recombination lifetime using drain current transients in floating-body SOI MOSFETs. The model is used in order to characterize submicron SOI devices, allowing a thorough investigation of technological parameters impact on floating-body-induced transient mechanisms.

Improved hot-carrier reliability of SOI transistors by deuterium passivation of defects at oxide/silicon interfaces

The effect of deuterium on hot-carrier reliability of fully processed 0.18 /spl mu/m silicon-on-insulator (SOI) devices is investigated. The improvement of device lifetime by a factor of 30 is achieved by passivating the interface defects with deuterium instead of hydrogen. The hydrogen/deuterium isotope effect (/spl gamma/), defined as the ratio of generation interface traps of a hydrogenated device to that of a deuterated one, shows strong dependence on the gate stress voltages (V/sub gs/). Increasing V/sub gs/ results in the decrease of /spl gamma/. These results suggest that the breaking of Si-H(D) bonds by channel electrons through the vibrational heating mechanism may play an important role in the degradation of deep submicron SOI devices.

Reduced reverse narrow channel effect in thin SOI nMOSFETs

The effects of narrow channel width on the threshold voltage of deep submicron silicon-on-insulator (SOI) nMOSFETs with LOCOS isolation have been investigated. The reverse narrow channel effect (RNCE) in SOI devices is found to be dependent on the thickness of the active silicon film. A thinner silicon film is found to depict less threshold voltage fall-off. These results can be explained by a reduced oxide/silicon interface area in the transistor width direction, thus the boron segregation due to silicon interstitials with high recombination rate is reduced.

Phase noise characteristics associated with low-frequency noise in submicron SOI MOSFET feedback oscillator for RF IC's

Phase noise in silicon-on-insulator (SOI) MOSFET feedback oscillators for RF IC applications is investigated. The observed correlation between the oscillator's high frequency phase noise and the transistor's low-frequency noise characteristics demonstrates that the phase noise overshoot still exists in partially-depleted (PD) floating body SOI nMOS Colpitts oscillators. These results suggest that kink-induced effects associated with low-frequency components of the signal are upconverted into the ideally kink-free high frequency domain operation mode of PD floating body SOI oscillators.