Submicrometer Technology Research Articles

A Reliability-Enhanced Differential Sensing Amplifier for Hybrid CMOS/MTJ Logic Circuits

Recently, hybrid logic circuits based on magnetic tunnel junctions (MTJs) have been widely investigated to realize zero standby power. However, such hybrid CMOS/MTJ logic circuits suffer from a severe sensing reliability due to the limited tunnel magnetoresistance ratio (TMR ≤ 150%) of the MTJ and the large process variation in the deep sub-micrometer technology node. In this paper, a novel differential sensing amplifier (DSA) is proposed, in which two PMOS transistors are added to connect the discharging branches and evaluation branches. Owing to the positive feedback realized by these two added PMOS transistors, it can achieve a large sensing margin. By using an industrial CMOS 40 nm design kit and a physics-based MTJ compact model, hybrid CMOS/MTJ simulations have been performed to demonstrate its functionality and evaluate its performance. Simulation results show that it can achieve a smaller sensing error rate of 9% in comparison with the previously proposed DSAs with a TMR ratio of 100% and process variation of 10%, while maintaining almost the same sensing delay of 74.5 ps and sensing energy of 1.92 fJ/bit.

A Highly Reliable, Dynamic Logic-Based Hybrid MTJ/CMOS Magnetic Full Adder for High-Performance and Low-Power Application

At deep sub-micrometer technology, CMOS circuits suffer from high leakage and have reliability issues due to process variation. Hybrid magnetic tunnel junction (MTJ)/CMOS circuits have been proposed to overcome these challenges. MTJs have zero standby power and are compatible with CMOS technology. In this article, a dynamic logic-based hybrid MTJ/CMOS magnetic full adder (MFA) has been proposed, which eliminates the error voltage appearing on output due to charge injection and clock feedthrough phenomenon, thereby enhancing the performance of MFA and making it more reliable. This effect is induced by the pMOS transistor, which is used as a switch to precharge the output nodes. The proposed MFA uses two dummy transistors, whose drain and source terminals are shorted to make them act as MOS capacitors, to absorb the error voltage introduced by the switch pMOS transistor due to charge injection and clock feedthrough, when turned OFF. Eliminating the error induced due to charge injection and clock feedthrough makes the amplification process faster and reduces the dynamic power consumption. Results are verified by performing transient and Monte Carlo simulations using cadence virtuoso with UMC 40 nm CMOS technology kit and compact model of perpendicular magnetic anisotropy (PMA) MTJ, which validates that the proposed MFA is highly reliable as it provides the error-free output and imparts better power–delay product (PDP) compared to previously proposed MFA.

Practical System-on-Chip Repeater Design With Hybrid Meta-Heuristic Techniques

This paper recommends a practical way to insert buffer and flop repeaters onto global signals of a complex system-on-chip (SoC). With the advent of deep sub-micrometer technology and new business environment, the market prefers a highly integrated SoC with fast design productivity and low development cost. We observed that many algorithms proposed in the prior arts, which used exact algorithms to optimize design solely for performance, power, and/or area, are no longer practical. With that, we introduced a hybrid meta-heuristic based flow, which combines meta-heuristic algorithm with different artificial intelligent algorithms such as exact and heuristic algorithms, to search for a near optimum buffer repeater insertion recipe, optimize the floor-plan pin placement, and then correctly insert flop repeater into the design. Our experiments on 10- and 14-nm SoC products showed that the flow managed to produce a “good enough” quality of repeater designs with fast turn-around-time and less design effort.

Transient Cell Supply Voltage Collapse Write Assist Using Charge Redistribution

This brief describes a charge redistribution transient cell supply voltage collapse write assist (CR-TVC-WA) for static random access memory. Although wordline underdrive read assist is a requisite for stable read operations in deep submicrometer technologies, it significantly degrades the write ability. To overcome this problem, a transient cell supply voltage $({V}_\mathrm{DD,CELL})$ collapse write assist (TVC-WA) method is widely used, but it consumes a large amount of energy. In the proposed CR-TVC-WA, the virtual cell supply and ground nodes are temporarily floated and connected to each other during the write operation. This improves the write ability and significantly reduces energy consumption. Simulation results indicate that the minimum operation voltage $({V}_\mathrm{MIN})$ is approximately 660 mV when the write operation is performed at 1 GHz and the extra write energy consumption (3.8 fJ) additionally required to satisfy the target yield $(6\sigma)$ is reduced by 46% compared with that in the conventional TVC-WA (7.0 fJ).

An Offset-Tolerant Dual-Reference-Voltage Sensing Scheme for Deep Submicrometer STT-RAM

Due to the increased process variation and reduced supply voltage in deep submicrometer technology nodes, an offset-tolerant sensing scheme has become essential. However, most offset-tolerant sensing schemes suffer from inherent performance degradation owing to multiple-stage sensing. In this paper, a dual $V_{\mathrm {ref}}$ sensing scheme (DVSS) that selectively uses an optimal $V_{\rm {ref}}$ between $V_{\rm {ref+}}$ and $V_{\rm {ref-}}$ is proposed. This scheme is tolerant to process variations, and can be used as a spin-transfer-torque random access memory. Because of no additional sensing stage, the offset-tolerant sensing is achieved without sacrificing the performance. The optimal $V_{\rm {ref}}$ is selected after fabrication, and the calibrated switch control bit, which contains $V_{{\rm {ref}}}$ selection information, is stored permanently in an on-chip nonvolatile latch. Monte Carlo HSPICE simulation results, using an industry-compatible 45-nm model parameters, show that the proposed DVSS achieves a read yield of 98.24% for 32 Mb (6.1 sigma) with $2\times $ faster sensing speed and $1.5\times $ lower read energy per bit compared with the state-of-the-art offset-tolerant sensing scheme.

Adaptive Multibit Crosstalk-Aware Error Control Coding Scheme for On-Chip Communication

The presence of different noise sources and continuous increase in crosstalk in the deep submicrometer technology raised concerns for on-chip communication reliability, leading to the incorporation of crosstalk avoidance techniques in error control coding schemes. This brief proposes joint crosstalk avoidance with adaptive error control scheme to reduce the power consumption by providing appropriate communication resiliency based on runtime noise level. By switching between shielding and duplication as the crosstalk avoidance technique and between hybrid automatic repeat request and forward error correction as the error control policies, three modes of error resiliencies are provided. The results show that, in reduced mode, the scheme achieves up to 25.3% power savings at 3-mm wire length as compared to the original nonadaptive scheme at the cost of only 3.4% power overhead in high protection mode.

A Review of CMOS Photodiode Modeling and the Role of the Lateral Photoresponse

The CMOS photodiode is the primary photosensing device used in solid-state image sensors. A review of significant CMOS photodiode models that can be found in the literature in recent years is presented here. We have focused on photocurrent models in one, two, and three dimensions, paying special attention to lateral current components. Lateral collection, particularly for small devices fabricated in deep submicrometer technologies, has been shown to be of utmost importance. Finally, several models to account for crosstalk effects are also described.

New Aspects of Fault Diagnosis of Nonlinear Analog Circuits

Abstract The paper is focused on nonlinear analog circuits, with the special attention paid to circuits comprising bipolar and MOS transistors manufactured in micrometer and submicrometer technology. The problem of fault diagnosis of this class of circuits is discussed, including locating faulty elements and evaluating their parameters. The paper deals with multiple parametric fault diagnosis using the simulation after test approach as well as detection and location of single catastrophic faults, using the simulation before test approach. The discussed methods are based on diagnostic test, leading to a system of nonlinear algebraic type equations, which are not given in explicit analytical form. An important and new aspect of the fault diagnosis is finding multiple solutions of the test equation, i.e. several sets of the parameters values that meet the test. Another new problems in this area are global fault diagnosis of technological parameters in CMOS circuits fabricated in submicrometer technology and testing the circuits having multiple DC operating points. To solve these problems several methods have been recently developed, which employ different concepts and mathematical tools of nonlinear analysis. In this paper they are sketched and illustrated. All the discussed methods are based on the homotopy (continuation) idea. It is shown that various versions of homotopy and combinations of the homotopy with some other mathematical algorithms lead to very powerful tools for fault diagnosis of nonlinear analog circuits. To trace the homotopy path which allows finding multiple solutions, the simplicial method, the restart method, the theory of linear complementarity problem and Lemke’s algorithm are employed. For illustration four numerical examples are given

A Theoretical Analysis of Fibonacci Coding Techniques on On-chip Data Bus

As VLSI technology has scaled down towards the Deep Sub-micrometer (DSM) technology the crosstalk delay is flattering a great part of the total delay of a circuit. In addition, the escalating of cross-coupling capacitances among on-chip bus wires on the identical metal layer generates a situation where the delay of a wire is effectively relying on the electrical status of its adjacent wires. Therefore the data patterns on the on-chip data bus will affect the crosstalk delay. In this Paper, the performance of the Fibonacci coding techniques with respect to transition energy and crosstalk delay has been carried out and compared between them. The simulation results show that the NFF, RF and CRF coding technique offers on average ∼50% energy savings and average ∼30% delay reduction. So the entire system performance increases while the crosstalk delay reduces. Hence, these coding techniques increase the speed of the bus and/or diminish the total energy dissipation.

Ant Colony Optimization-Based Fault-Aware Routing in Mesh-Based Network-on-Chip Systems

The advanced deep submicrometer technology increases the risk of failure for on-chip components. In advanced network-on-chip (NoC) systems, the failure constrains the on-chip bandwidth and network throughput. Fault-tolerant routing algorithms aim to alleviate the impact on performance. However, few works have integrated the congestion-, deadlock-, and fault-awareness information in channel evaluation function to avoid the hotspot around the faulty router. To solve this problem, we propose the ant colony optimization-based fault-aware routing (ACO-FAR) algorithm for load balancing in faulty networks. The behavior of an ant colony while facing an obstacle (failure in NoC) can be described in three steps: 1) encounter; 2) search; and 3) select. We implement the corresponding mechanisms as: 1) notification of fault information; 2) path searching mechanism; and 3) path selecting mechanism. With proposed ACO-FAR, the router can evaluate the available paths and detour packets through a less-congested fault-free path. The simulation results show that this paper has higher throughput than related works by 29.1%–66.5%. In addition, ACO-FAR can reduce the undelivered packet ratio to 0.5%–0.02% and balance the distribution of traffic flow in the faulty network.

Separated Precharge Sensing Amplifier for Deep Submicrometer MTJ/CMOS Hybrid Logic Circuits

Magnetic tunnel junction (MTJ) embedded in complementary metal-oxide-semiconductor (CMOS) has been considered as one of the potentially powerful solutions to build up nonvolatile memory and logic circuits. It possesses many intrinsic merits, such as high speed, instant on/off, good scalability and low-leakage power, and promises to extend the Moore's law. A critical issue in this hybrid MTJ/CMOS structure is the reliable integration of MTJ electric signals to CMOS electronics, especially for the deep submicrometer technology nodes (e.g., 28 nm) in presence of low supply voltage and serious process variations. In this paper, we propose a new sensing amplifier, named separated precharge sense amplifier. This circuit, by separating the discharging and evaluation stages of the sensing operation, can operate at a lower supply voltage (<;1.0 V) and reduces the effects of process variations as technology scales, thereby providing higher sensing reliability compared with the previously proposed solutions while preserving the high-speed and low-power consumption. Transient and Monte-Carlo statistical simulations are performed to demonstrate its sensing performance.

Design Framework to Overcome Aging Degradation of the 16 nm VLSI Technology Circuits

Intensive scaling for VLSI circuits is a key factor for gaining outstanding performance. However, this scaling has huge negative impact on the circuit reliability, as it increases the undesired effect of aging degradation on ultradeep submicrometer technologies. Nowadays, Bias Temperature Instability (BTI) aging process has a major negative impact on VLSI circuits reliability. This paper presents a comprehensive framework that assists in designing the fortified VLSI circuits against BTI aging degradation. The framework contains: 1) the novel circuit level techniques that eliminate the effect of BTI (these techniques successfully decrease the power dissipation by 36% and enhance the reliability of VLSI circuits); 2) the evaluation of the reliability of all circuit level techniques used to eliminate BTI aging degradation for 16 nm CMOS technology; and 3) the comparison between the efficiency of all circuit level techniques in terms of power consumption and area.

New Crosstalk Avoidance Codes Based on a Novel Pattern Classification

The crosstalk delay associated with global on-chip interconnects becomes more severe in deep submicrometer technology, and hence can greatly affect the overall system performance. Based on a delay model proposed by Sotiriadis , transition patterns over a bus can be classified according to their delays. Using this classification, crosstalk avoidance codes (CACs) have been proposed to alleviate the crosstalk delays by restricting the transition patterns on a bus. In this paper, we first propose a new classification of transition patterns, and then devise a new family of CACs based on this classification. In comparison to the previous classification, our classification has more classes and the delays of its classes do not overlap, both leading to more accurate control of delays. Our new family of CACs includes some previously proposed codes as well as new codes with reduced delays and improved throughput. Thus, this new family of CACs provides a wider variety of tradeoffs between bus delay and efficiency. Finally, since our analytical approach to the classification and CACs treats the technology-dependent parameters as variables, our approach can be easily adapted to a wide variety of technologies.

New Approach to VLSI Buffer Modeling, Considering Overshooting Effect

In this brief, we use the alpha power law model for MOS devices to reach a more accurate modeling of CMOS buffers in very deep submicrometer technologies. We derive alpha model parameters of a CMOS buffer for 90-, 65-, and 45-nm technologies using HSPICE simulations. By analytical efforts we find the output resistance of a minimum-size buffer and compare it with those extracted from HSPICE simulations. We propose a new model for the output resistance of a given-size buffer in any technology, which demonstrates 3% error on average as opposed to the conventional model. Also a new buffer resistance is proposed analytically and numerically to calculate the crosstalk for interconnect analysis applications. In addition, we propose a model for the transfer function zero generated by the gate-drain capacitances of MOS transistors, which cause the overshooting effect, and develop an accurate expression for modeling this phenomenon. As the final point, together with the input-to-output capacitance, the equivalent output resistors present a simple and accurate macromodel for the CMOS buffer.

A Substrate-and-Gate Triggering NMOS Device for High ESD Reliability in Deep Submicrometer Technology

A substrate-and-gate triggering scheme which utilizes dynamic threshold principle is proposed for an ESD NMOS structure. This scheme enhances the device reliability performance in terms of higher second breakdown current and both reduced holding voltage/triggering voltage as well as elimination of gate over driven effect. The simple resistance and RC substrate-and-gate triggering NMOS structure with various resistance/capacitance values totally exhibit superior ESD reliability than the gate-grounded NMOS (GGNMOS) devices by 18~29%. The substrate-and-gate triggering scheme in combination with special substrate pickup styles also shows excellent enhancement when compared with the GGNMOS cases of the same pickup styles. The substrate-and-gate triggering NMOS with butting substrate pickup style is better than the general butting case by 28~30%, whereas the substrate-and-gate triggering NMOS with inserted substrate pickup style is 3.5 times superior to the general inserted case.

Read-Preferred SRAM Cell With Write-Assist Circuit Using Back-Gate ETSOI Transistors in 22-nm Technology

The degradation of the read stability and write ability of static random-access memory (SRAM) is becoming a critical problem in deep submicrometer technology. To solve this problem, there are many SRAM cell design options such as preferred cells and assist circuits. In addition, extremely thin silicon-on-insulator (ETSOI) with a buried oxide offers an independent back-gate control. In this paper, previously proposed SRAM back-gate-assist circuit schemes are analyzed. From this, we propose a read-preferred SRAM cell with a write-assist circuit using the back-gate ETSOI. The proposed write-assist circuit minimizes the dynamic power overhead and satisfies a sufficient cell sigma in all cells during the read and write operations.

Test Pattern Generation of Relaxed $n$-Detect Test Sets

While defect oriented testing in digital circuits is a hard process, detecting a modeled fault more than one time has been shown to result in high defect coverage. Previous work shows that such test sets, known as multiple detect or n-detect test sets, are of increased quality for a number of common defects in deep sub-micrometer technologies. Method for multiple detect test generation usually produce fully specified test patterns. This limits their usage in a number of important applications such as low power test and test compression. This work proposes a systematic methodology for identifying a large number of bits that can be unspecified in a multiple detect (n-detect) test set, while preserving the original fault coverage. The experimental results demonstrate that the number of specified bits in, even compact, n-detect test sets can be significantly reduced without any impact on the n-detect property. Additionally, in many cases, the size of the test set is reduced.

Signal Integrity Analysis of High-Speed Interconnects by Using Nonconformal Domain Decomposition Method

3-D interconnect techniques in multilayer very large scale integration design, such as stacked layers and various chip-stacking systems, have paved the way for the improvement of integrated circuit density and operation speed. However, these techniques often accompany with impedance discontinuities that induce signal integrity (SI)/power integrity and electromagnetic interference effects. Consequently, SI analysis serves as one of the key guidelines of chip-package-board design in deep submicrometer technology. However, full-wave numerical analysis of 3-D high-speed and high-density interconnects is also considered to be a great challenge. In this paper, a nonconformal domain decomposition method with second-order transmission condition for SI analysis of high-speed interconnects on a multiscale multilayer printed circuit board is presented. The accuracy and robustness of the proposed method are first witnessed by modeling a six-layer two-trace differential pair. Then we study a 14-layer 16-trace interconnect model to demonstrate the efficiency of the method. Eye diagrams of the two models are also presented in the time-domain SI analysis.

SVFD: A Versatile Online Fault Detection Scheme via Checking of Stability Violation

In ultra-deep submicrometer technology, soft errors and device aging are two of the paramount reliability concerns. Although many studies have been done to tackle the two challenges, most take them separately so far, thereby failing to reach better performance-cost tradeoffs. To support a more efficient design tradeoff, we propose a unified fault detection scheme—stability violation-based fault detection (SVFD), by which the soft errors (both single event upset and single event transient), aging delay, and delay faults can be uniformly dealt with. SVFD grounds on a new fault model, stability violation, derived from analysis of signal behavior. SVFD has been validated by conducting a set of intensive Hspice simulations targeting the next-generation 32-nm CMOS technology. An application of SVFD to a floating-point unit (FPU) is also evaluated. Experimental results show that SVFD has more versatile fault detection capability for fault detection than several schemes recently proposed at comparable overhead in terms of area, power, and performance.

Evaluating Carbon Nanotube Global Interconnects for Chip Multiprocessor Applications

In ultra-deep submicrometer (UDSM) technologies, the current paradigm of using copper (Cu) interconnects for on-chip global communication is rapidly becoming a serious performance bottleneck. In this paper, we perform a system level evaluation of Carbon Nanotube (CNT) interconnect alternatives that may replace conventional Cu interconnects. Our analysis explores the impact of using CNT global interconnects on the performance and energy consumption of several multi-core chip multiprocessor (CMP) applications. Results from our analysis indicate that with improvements in fabrication technology, CNT-based global interconnects can significantly outperform Cu-based global interconnects.