A Substrate-and-Gate Triggering NMOS Device for High ESD Reliability in Deep Submicrometer Technology

Chih-Yao Huang,Fu-Chien Chiu

doi:10.1155/2013/905686

Abstract

A substrate-and-gate triggering scheme which utilizes dynamic threshold principle is proposed for an ESD NMOS structure. This scheme enhances the device reliability performance in terms of higher second breakdown current and both reduced holding voltage/triggering voltage as well as elimination of gate over driven effect. The simple resistance and RC substrate-and-gate triggering NMOS structure with various resistance/capacitance values totally exhibit superior ESD reliability than the gate-grounded NMOS (GGNMOS) devices by 18~29%. The substrate-and-gate triggering scheme in combination with special substrate pickup styles also shows excellent enhancement when compared with the GGNMOS cases of the same pickup styles. The substrate-and-gate triggering NMOS with butting substrate pickup style is better than the general butting case by 28~30%, whereas the substrate-and-gate triggering NMOS with inserted substrate pickup style is 3.5 times superior to the general inserted case.

Highlights

Electrostatic discharge (ESD) issue has become a more serious device reliability problem in semiconductor components and systems
Gate-coupling technique can improve the ESD capability, it still has gate overdriven effect if the gate voltage coupled is much larger than its threshold voltage, and this leads to serious ESD degradation
The trigger point voltages Vt1 are suppressed to about 4.9 V and the holding voltage VH to 3 V owing to the gate and substrate triggering connection. This implies that the parasitic BJT turns on more efficiently for the substrate-and-gate triggering NMOS (SGTNMOS) cases than the gategrounded NMOS (GGNMOS)

Summary

Introduction

Electrostatic discharge (ESD) issue has become a more serious device reliability problem in semiconductor components and systems. ESD NMOS protection devices usually need the large width size to deal with ESD events. This results in multifinger layout style which is commonly used in practical IC I/O area. It has a critical drawback which is not favorable for the ESD protection requirement. Inserted or butting substrate pickups in the source diffusion region of the ESD NMOS device in deep submicrometer technology degraded ESD reliability seriously. Such layout style has been strictly prohibited in practical ESD design applications by the technology design rules. Effect in eliminating the gate overdriven issue that often happens in the gate-coupling NMOS

Substrate-and-Gate Triggering NMOS Scheme

Results and Discussion

D Iinject

GGNMOS

Conclusions