Comparison of drain-induced barrier-lowering in short-channel NMOS and PMOS devices at 77 K

Abstract

This paper presents detailed comparisons between the room temperature and liquid nitrogen temperature experimental and 2-D simulation DIBL results in varying channel lengths NMOS and PMOS devices. The results in PMOS devices showed that DIBL is always worse at 300 than at 77 K. However, for NMOS devices, a unique DIBL temperature-dependent feature was observed, that is, DIBL is improved for devices with L < 0.6 and L > 1.2 μm, but is worse for devices in which 0.6 < L < 1.2 μm. Investigation of the physical mechanisms for explaining the above phenomenon in both types of MOS devices was carried out with the new version of the 2-D device numerical simulation program MINIMOS 4.0, that includes device modeling at cryogenic temperatures. The simulation results show that: (a) the major difference between NMOS and PMOS devices structure is the additional B-ion channel doping which tends to prevent punch-through in the sub-surface region for shorter channel NMOS devices, but forms a buried p-type sub-surface channel for shorter channel PMOS devices; and (b) lowering the temperature from 300 to 77 K caused the channel current path to be pushed back towards the channel surface for both NMOS and PMOS devices due to the freeze-out effect in the substrate. Therefore, the observed DIBL characteristics could be explained physically by the combination of the different source drain junction potential profiles between NMOS and PMOS devices, and the different current flow paths at 300 and 77 K.