Development of 6H-SiC CMOS Transistors for Insertion into a 350 deg C Operational Amplifier

Abstract

Abstract : Wafers with epitaxial layers have been grown for both n-channel and p-channel 6H-SiC MOSFETs. The device fabrication for each of these devices has been initiated and is on-going. Both types of devices will utilize ion implanted source and drain wells and will have molybdenum gate contacts that overlap the implanted wells. The same interdigitated mask design will be used for both of the devices. Eight wafers for p-channel devices are being held until the first batch of these devices is completed. Device parameter measurements have been made on n-channel MOSFET devices that were fabricated prior to this contract. These parameters will be used to simulate circuits using Simulation Program with Integrated Circuit Emphasis (SPICE). Three approaches have been examined for designing circuit using both NMOS and PMOS transistors in a complementary design. These include a hybrid approach that uses NMOS and PMOS devices fabricated on separate wafers, a shared substrate approach that uses an enhancement-mode PMOS device and a depletion-mode NMOS device, and a traditional single substrate CMOS approach utilizing PMOS and NMOS devices that both operate in enhancement-mode.