Practical System-on-Chip Repeater Design With Hybrid Meta-Heuristic Techniques

Abstract

This paper recommends a practical way to insert buffer and flop repeaters onto global signals of a complex system-on-chip (SoC). With the advent of deep sub-micrometer technology and new business environment, the market prefers a highly integrated SoC with fast design productivity and low development cost. We observed that many algorithms proposed in the prior arts, which used exact algorithms to optimize design solely for performance, power, and/or area, are no longer practical. With that, we introduced a hybrid meta-heuristic based flow, which combines meta-heuristic algorithm with different artificial intelligent algorithms such as exact and heuristic algorithms, to search for a near optimum buffer repeater insertion recipe, optimize the floor-plan pin placement, and then correctly insert flop repeater into the design. Our experiments on 10- and 14-nm SoC products showed that the flow managed to produce a “good enough” quality of repeater designs with fast turn-around-time and less design effort.