Block Level Implementation Of Orca Top Using H-Technique

Abstract

The design of a clock tree is a critical aspect of a system-on-chip (SoC) design, as it determines the timing characteristics of the chip and impacts its overall performance. The ORCA Top technique is a clock network synthesis tool that has been developed to efficiently design clock trees for SoCs. The main objective of this project is to design a highly integrated but low power SoC with fast design productivity and low development cost. To achieve this objective, the project introduces a flexible Block Level clock network topology and a synthesis algorithm that uses an H-Technique to search for a near-optimum solution in a shorter turn-around time.The design was implemented on a 28nm System-on-Chip product, and the results showed that the proposed topology and algorithm managed to produce an average of 16.98% better global skew and 42.75% less divergence on critical clock paths. Additionally, the clock balancing phase was 64.5% shorter compared to a conventional ASIC methodology used earlier. These results indicate that the proposed approach can effectively optimize the clock tree design for improved performance while reducing power consumption and overall design cost. In summary, the project demonstrates a successful implementation of a flexible Block Level clock network topology using the ORCA Top technique, which can significantly improve the performance of a highly integrated and low power SoC with fast design productivity and low development cost.