Low power SOC in deep-submicron era

Abstract

Summary form only given. As system-on-chip (SOC) technology advances, it is becoming possible to integrate all processing elements into a single SOC, including basic transistors/gates, various processor cores, memory cells, and analog macros. Today is truly an SOC era, where SOC designers must consider not only HW design, but also SW design. In the history of SOC technology, there has been a prominent improvement toward reducing operating power by means of decreasing feature size and lowering operating voltage. But, it seems that there is a physical limitation to reducing stand-by current, which is crucial for mobile devices, while maintaining performance. In the area of mobile SOC design with deep-submicron technology, it becomes a complex task to simultaneously pursue the two goals of improving the performance and reducing stand-by current. In this tutorial, we introduce and evaluate a variety of methodologies to achieve a low power and high performance SOC design.