Submicron Technology Research Articles

Dynamic Power Reduction in Digital VLSI Circuits Using Stacked LCNMOS

In deep submicron technologies, leakage power becomes a key for a low power design due to its ever increasing proportion in chips total power consumption. Power dissipation is an important consideration in the design of CMOS VLSI circuits. High power consumption leads to reduction in battery life in case of battery powered applications and affects reliability packaging and cooling costs. We propose a technique called Stacked LCNMOS for designing CMOS gates. LCNMOS technique significantly cuts down the leakage current without increasing switching power dissipation. LCNMOS, a technique to tackle the leakage problem in all digital circuits, uses single additional Leakage Control Transistor (LCT) driven by the output from the pull up and pull down networks, which is placed in a path from pull down network to ground. This LCT provides the additional resistance thereby reducing leakage current in path from supply to ground. In stacked LCNMOS technique, every transistor in the network is duplicated with both the transistors bearing half the original transistor width. It overcomes the limitation of sleep technique by retaining states. All the performances has been investigated using 90nm technology at one voltage and evaluated by the comparison of the simulation result obtained from T-SPICE

A Review on Various Leakage Power Reduction Techniques in Deep Submicron Technologies in CMOS VLSI Circuits

A Review on Various Leakage Power Reduction Techniques in Deep Submicron Technologies in CMOS VLSI Circuits

A novel design of high performance1-bit adder circuit at deep sub-micron technology

In this paper, the design of hybrid 1-bit full adder circuit using both pass transistor and CMOS logic was implemented. Performance pa-rameters such as power, delay, and PDP were compared with the existing designs such as complementary pass-transistor logic, transmis-sion gate adder. At 0.4V supply at 22nm technology, the average power consumption is 1. 525 uW was found to be extremely low with moderately low delay 90. 25 ps and PDP found to be 0.137 fJ. The present implementation has very good improvement in terms of delay, power and power delay product when compared to the existing hybrid 1-bit full adders. Also the number of transistors has been reduced to 13 where as the existiing hybrid full adder circuit has 16 transistors. The proposed circuit was implemented using mentor graphics tool in 45nm, 32nm and 22nm technologies with different supply voltages.

Runtime hardware Trojan monitors through modeling burst mode communication using formal verification

Globalization trends in integrated circuit (IC) design using deep sub-micron (DSM) technologies are leading to increased vulnerability against malicious intrusions. Various techniques have been proposed to detect such threats during design or testing phases of ICs. However, due to infinitely many possibilities of Trojans, there exists a possibility that some of these intrusions go undetected. Therefore, runtime Trojan detection techniques are needed to detect the Trojans for complete operation lifetime as a last line of defense. In this paper, we proposed a generic methodology, which leverages the burst mode communication protocol, to detect the intrusions during runtime. Our methodology has three phases: 1) behavioral modeling of design specifications along with its verification using linear temporal logic (LTL) in the model checker. 2) Counterexamples generated in phase 1 are used to insert run-time monitors at vulnerable paths. 3) Embed run-time monitors into the system and validate it. Unlike the other state-of-the-art techniques, the proposed methodology can be easily used to design the runtime monitoring setup without having netlist information of IP modules. We validated our approach by applying it on the AES Trojan benchmarks that utilize intermodule interface to communicate with other modules in the system on chip (SoC).

An accurate behavioral model for single-photon avalanche diode statistical performance simulation

An accurate behavioral model is presented to simulate important statistical performance of single-photon avalanche diodes (SPADs), such as dark count and after-pulsing noise. The derived simulation model takes into account all important generation mechanisms of the two kinds of noise. For the first time, thermal agitation, trap-assisted tunneling and band-to-band tunneling mechanisms are simultaneously incorporated in the simulation model to evaluate dark count behavior of SPADs fabricated in deep sub-micron CMOS technology. Meanwhile, a complete carrier trapping and de-trapping process is considered in afterpulsing model and a simple analytical expression is derived to estimate after-pulsing probability. In particular, the key model parameters of avalanche triggering probability and electric field dependence of excess bias voltage are extracted from Geiger-mode TCAD simulation and this behavioral simulation model doesn't include any empirical parameters. The developed SPAD model is implemented in Verilog-A behavioral hardware description language and successfully operated on commercial Cadence Spectre simulator, showing good universality and compatibility. The model simulation results are in a good accordance with the test data, validating high simulation accuracy.

Formation of carbon films as the subgate dielectric of GaAs microcircuits on Si-substrates

The technological aspects of the formation of thin α-C:H carbon films, the peculiarities of the ion-plasma Q-DLTS spectra of heterostructures α-C:H-Si and α-C: H-GaAs are considered, and activation energy, cross-trapping and density of deep traps, responsible for charge state, are determined. The correlation between the technological regimes of the α-C:H film formation and trap density is established. The technological methods and regimes that allow obtaining structures with a relatively small surface state density N ss ≤10 12 cm -2 are determined. This allows using these structures as a subgate dielectric in GaAs-CMOS structures of LSICs. Low-temperature epitaxy of GaAs-layers on silicon substrates with the use of excimer lasers is developed, where germanium film acts as a buffer layer between Si and GaAs. The technology of carbon films formation by deposition from the carbon target is developed. The use of carbon films as a subgate dielectric allows the formation of CMOS-transistors on GaAs-epilayers with symmetric threshold voltages, which opens a new direction for the development of the sub-micron technology of LSICs and enables to increase the LSICs speed and reduce their production cost.

Adaptive Multi-Voltage Scaling with Utilization Prediction for Energy-Efficient Wireless NoC

Networks-on-Chip (NoCs) are fast becoming the de-facto communication infrastructures in chip multi-processors for large-scale applications. Wireless NoCs (WNoCs) offer a promising solution to reduce the long-distance communication bottlenecks of conventional NoCs by augmenting them with single hop, long-range wireless links. However, power consumption in routers and network elements still remains considerably high at ultra-deep submicron technologies. Analysis of network resources for several benchmarks shows that, utilization is application dependent and the desired performance can be achieved even without operating all resources at maximum specifications. In this work, we propose an energy-efficient WNoC architecture using Adaptive Multi-Voltage Scaling (AMS) to dynamically vary supply voltage for NoC routers and Wireless Interfaces (WIs) without adversely impacting performance. The proposed scheme uses a probabilistic model to predict router utilization during different application phases and scales voltage accordingly. It further reduces network energy by power-gating WIs that are not engaged in active communication to minimize their power consumption. We present detailed utilization estimation procedure, AMS control mechanism, and its hardware implementation. It saves up to 56 percent in network packet energy consumption and 62.50 percent power consumption in WIs for 256 core system as compared to baseline architectures without incurring significant performance penalty and area overheads.

Energy efficient parallel hybrid adder architecture for 3X generation in radix-8 booth encoding

The need for hard (3X) multiple generation in radix-8 booth encoding increases the complexity of partial product generation and the latency of the multiplier. The source of delay is primarily the propagation of carry signals. A variety of carry propagate adder architectures have been studied to overcome this drawback. In this paper, we propose a hybrid adder architecture that precomputes the simultaneous generation of pseudo carry signals by exploiting the symmetry of 3X multiple and the final carry generation using Ling prefix network. As the Ling adder in the carry path reduces the complexity, the proposed adder results in significant improvement in the power delay product ($${\sim }$$25–55%) compared to state of the art 64 bit adders. This adder decreases the number of logic gates in the critical path, leading to a reduction in static power consumption. As a design metric, it is necessary to minimize the energy dissipation of logic modules, the results indicate that the proposed hybrid adder would fulfil the requirements of processors in deep sub-micron VLSI technology.

Scalable [formula omitted]-power law based MOSFET model for characterization of ultra deep submicron digital integrated circuit design

Analytical circuit design, optimization, characterization and development of design methodology for digital circuits using nanoscale CMOS devices require compact equations. Such equations need to include first order short channel phenomena relevant to the nanoscale technology nodes being used. The present paper demonstrates that α-power model can be updated to include velocity overshoot necessary to characterize devices at ultradeep submicron technology nodes. Further, the three α-power model parameters (velocity saturation index α, transconductance parameter K1 and threshold voltage Vth) expressing MOSFET drain current has been expressed in terms of predictive technology model (PTM) parameters. Representative basic CMOS cells belonging both to inverter and transmission gate categories have been analytically characterized using the updated α-power model up to ultradeep submicron technology node with BSIM verification. It has been shown that consideration of velocity overshoot is important for accurate prediction below 40nm.

Fault-Tolerant Dynamic Task Mapping and Scheduling for Network-on-Chip-Based Multicore Platform

In Network-on-Chip (NoC)-based multicore systems, task allocation and scheduling are known to be important problems, as they affect the performance of applications in terms of energy consumption and timing. Advancement of deep submicron technology has made it possible to scale the transistor feature size to the nanometer range, which has enabled multiple processing elements to be integrated onto a single chip. On the flipside, it has made the integrated entities on the chip more susceptible to different faults. Although a significant amount of work has been done in the domain of fault-tolerant mapping and scheduling, existing algorithms either precompute reconfigured mapping solutions at design time while anticipating fault(s) scenarios or adopt a hybrid approach wherein a part of the fault mitigation strategy relies on the design-time solution. The complexity of the problem rises further for real-time dynamic systems where new applications can arrive in the multicore platform at any time instant. For real-time systems, the validity of computation depends both on the correctness of results and on temporal constraint satisfaction. This article presents an improved fault-tolerant dynamic solution to the integrated problem of application mapping and scheduling for NoC-based multicore platforms. The developed algorithm provides a unified mapping and scheduling method for real-time systems focusing on meeting application deadlines and minimizing communication energy. A predictive model has been used to determine the failure-prone cores in the system for which a fault-tolerant resource allocation with task redundancy has been performed. By selectively using a task replication policy, the reliability of the application, executing on a given NoC platform, is improved. A detailed evaluation of the performance of the proposed algorithm has been conducted for both real and synthetic applications. When compared with other fault-tolerant algorithms reported in the literature, performance of the proposed algorithm shows an average reduction of 56.95% in task re-execution time overhead and an average improvement of 31% in communication energy. Further, for time-constrained tasks, deadline satisfaction has also been achieved for most of the test cases by the developed algorithm, whereas the techniques reported in the literature failed to meet deadline in about 45% test cases.

20–25 Gbit/s low-power inductor-less single-chip optical receiver and transmitter frontend in 28 nm digital CMOS

The design of an analog frontend including a receiver amplifier (RX) and laser diode driver (LDD) for optical communication system is described. The RX consists of a transimpedance amplifier, a limiting amplifier, and an output buffer (BUF). An offset compensation and common-mode control circuit is designed using switched-capacitor technique to save chip area, provides continuous reduction of the offset in the RX. Active-peaking methods are used to enhance the bandwidth and gain. The very low gate-oxide breakdown voltage of transistors in deep sub-micron technologies is overcome in the LDD by implementing a topology which has the amplifier placed in a floating well. It comprises a level shifter, a pre-amplifier, and the driver stage. The single-chip frontend, fabricated in a 28 nm bulk-digital complementary metal–oxide–semiconductor (CMOS) process has a total active area of 0.003 mm2, is among the smallest optical frontends. Without the BUF, which consumes 8 mW from a separate supply, the RX power consumption is 21 mW, while the LDD consumes 32 mW. Small-signal gain and bandwidth are measured. A photo diode and laser diode are bonded to the chip on a test-printed circuit board. Electro-optical measurements show an error-free detection with a bit error rate of 10−12at 20 Gbit/s of the RX at and a 25 Gbit/s transmission of the LDD.

Standby and dynamic power minimization using enhanced hybrid power gating structure for deep-submicron CMOS VLSI

Scaling down of CMOS Technology reduces supply voltage which helps evade device botch caused by high electric fields in the conducting channel under the gate and gate oxide. Voltage scaling lessens circuit power consumption but increases delay of logic gates badly and the performance is degraded to a large extent in deep submicron CMOS VLSI circuits. In order to achieve good performance, the delay of logic gates has to be decreased. Circuits for trimming down of leakage power in sub-micron technologies also increase the dynamic power to a large extent. In this paper, a novel hybrid MTCMOS technique is proposed to reduce the enormous delay in gates due to sleep transistors; also, static power consumption is reduced without much affecting the dynamic power consumption of the circuit. For the 16-bit Ripple Carry Adder, the proposed technique can save up to 76.8% of static power consumption and 55.5% of dynamic power consumption also.

Aging signature properties and an efficient signature determination tool for online monitoring

Increased reliability problems in deep sub-micron CMOS technologies have led to a dramatic decrease of lifetime of analog integrated circuits. To palliate this problem, several reliability-aware design approaches have been developed. Reconfigurable circuit design is one of those approaches, which is based on reconfiguring the circuit considering degradation in circuit performances. Sense & React (S & R) approach is the well-known reconfigurable design approach, where degradation in circuit performances are sensed and a pre-established recovery operation is applied to heal the circuit. In practice, indirect measurements are preferred during sense operation, in which electrical quantities are measured in order to determine time to recovery. Determination of the time to recover is the most critical part of a S & R system. One or more circuit variables are selected out of all measurable circuit quantities. The selected signature should have some attributes to be used as the aging signature to reduce the measurement cost. However, efficient aging signature properties have not been defined in the literature yet. Moreover, the designer determines the aging signature manually by performing an iterative search and evaluation on aging simulation results, and there is no tool to ease this time consuming process. This paper clearly describes the aging signature properties and proposes an automatic signature selection tool that determines the most efficient signature for sense operation.

Path-Diversity-Aware Fault-Tolerant Routing Algorithm for Network-on-Chip Systems

Network-on-Chip (NoC) is the regular and scalable design architecture for chip multiprocessor (CMP) systems. With the increasing number of cores and the scaling of network in deep submicron (DSM) technology, the NoC systems become subject to manufacturing defects and have low production yield. Due to the fault issues, the reduction in the number of available routing paths for packet delivery may cause severe traffic congestion and even to a system crash. Therefore, the fault-tolerant routing algorithm is desired to maintain the correctness of system functionality. To overcome fault problems, conventional fault-tolerant routing algorithms employ fault information and buffer occupancy information of the local regions. However, the information only provides a limited view of traffic in the network, which still results in heavy traffic congestion. To achieve fault-resilient packet delivery and traffic balancing, this work proposes a Path-Diversity-Aware Fault-Tolerant Routing ( PDA-FTR ) algorithm, which simultaneously considers path diversity information and buffer information. Compared with other fault-tolerant routing algorithms, the proposed work can improve average saturation throughput by 175 percent with only 8.9 percent average area overhead and 7.1 percent average power overhead.

Problems and Properties of a Current Amplifier When Realized in Ultra Deep Sub-micron Technology

Problems and Properties of a Current Amplifier When Realized in Ultra Deep Sub-micron Technology

Comparative Analysis of Design of Low Power Full Adder Structures for Deep Sub-Micron Technology

Comparative Analysis of Design of Low Power Full Adder Structures for Deep Sub-Micron Technology

Comparative Simulation Analysis of Process Parameter Variations in 20 nm Triangular FinFET

Technology scaling below 22 nm has brought several detrimental effects such as increased short channel effects (SCEs) and leakage currents. In deep submicron technology further scaling in gate length and oxide thickness can be achieved by changing the device structure of MOSFET. For 10–30 nm channel length multigate MOSFETs have been considered as most promising devices and FinFETs are the leading multigate MOSFET devices. Process parameters can be varied to obtain the desired performance of the FinFET device. In this paper, evaluation of on-off current ratio (Ion/Ioff), subthreshold swing (SS) and Drain Induced Barrier Lowering (DIBL) for different process parameters, that is, doping concentration (1015/cm3 to 1018/cm3), oxide thickness (0.5 nm and 1 nm), and fin height (10 nm to 40 nm), has been presented for 20 nm triangular FinFET device. Density gradient model used in design simulation incorporates the considerable quantum effects and provides more practical environment for device simulation. Simulation result shows that fin shape has great impact on FinFET performance and triangular fin shape leads to reduction in leakage current and SCEs. Comparative analysis of simulation results has been investigated to observe the impact of process parameters on the performance of designed FinFET.

Neural Imaging Using Single-Photon Avalanche Diodes.

Introduction:This paper analyses the ability of single-photon avalanche diodes (SPADs) for neural imaging. The current trend in the production of SPADs moves toward the minimum dark count rate (DCR) and maximum photon detection probability (PDP). Moreover, the jitter response which is the main measurement characteristic for the timing uncertainty is progressing.Methods:The neural imaging process using SPADs can be performed by means of florescence lifetime imaging (FLIM), time correlated single-photon counting (TCSPC), positron emission tomography (PET), and single-photon emission computed tomography (SPECT).Results:This trend will result in more precise neural imaging cameras. While achieving low DCR SPADs is difficult in deep submicron technologies because of using higher doping profiles, higher PDPs are reported in green and blue part of light. Furthermore, the number of pixels integrated in the same chip is increasing with the technology progress which can result in the higher resolution of imaging.Conclusion:This study proposes implemented SPADs in Deep-submicron technologies to be used in neural imaging cameras, due to the small size pixels and higher timing accuracies.

On Improving the Performance of Dynamic DCVSL Circuits

This contribution aims at improving the performance of Dynamic Differential Cascode Voltage Switch Logic (Dy-DCVSL) and Enhanced Dynamic Differential Cascode Voltage Switch Logic (EDCVSL) and suggests three architectures for the same. The first architecture uses transmission gates (TG) to reduce the logic tree depth and width, which results in speed improvement. As leakage is a dominant issue in lower technology nodes, the second architecture is proposed by adapting the leakage control technique (LECTOR) in Dy-DCVSL and EDCVSL. The third proposed architecture combines features of both the first and the second architectures. The operation of the proposed architectures has been verified through extensive simulations with different CMOS submicron technology nodes (90 nm, 65 nm, and 45 nm). The delay of the gates based on the first architecture remains almost the same for different functionalities. It is also observed that Dy-DCVSL gates are 1.6 to 1.4 times faster than their conventional counterpart. The gates based on the second architecture show a maximum of 74.3% leakage power reduction. Also, it is observed that the percentage of reduction in leakage power increases with technology scaling. Lastly, the gates based on the third architecture achieve similar leakage power reduction values to the second one but are not able to exhibit the same speed advantage as achieved with the first architecture.

Comprehensive understanding of dark count mechanisms of single-photon avalanche diodes fabricated in deep sub-micron CMOS technologies

The dark count noise mechanisms of single-photon avalanche diodes (SPADs) fabricated in deep sub-micron (DSM) CMOS technologies are investigated in depth. An electric field dependence of tunneling model combined with carrier thermal generation is established for dark count rate (DCR) prediction. Applying the crucial parameters provided by Geiger mode TCAD simulation such as avalanche triggering probability and electric field distribution in the SPAD avalanche region, the individual contribution of each noise source to DCR is calculated for several SPADs in DSM CMOS technologies. The model calculation results reveal that the trap-assisted tunneling is the main DCR generation source for these DSM CMOS SPADs. With the increase of doping levels in the device avalanche region, the band-to-band tunneling will be the dominant factor that could lead to the higher DCR in scaled DSM CMOS technologies.