Dynamic Power Reduction in Digital VLSI Circuits Using Stacked LCNMOS

Abstract

In deep submicron technologies, leakage power becomes a key for a low power design due to its ever increasing proportion in chips total power consumption. Power dissipation is an important consideration in the design of CMOS VLSI circuits. High power consumption leads to reduction in battery life in case of battery powered applications and affects reliability packaging and cooling costs. We propose a technique called Stacked LCNMOS for designing CMOS gates. LCNMOS technique significantly cuts down the leakage current without increasing switching power dissipation. LCNMOS, a technique to tackle the leakage problem in all digital circuits, uses single additional Leakage Control Transistor (LCT) driven by the output from the pull up and pull down networks, which is placed in a path from pull down network to ground. This LCT provides the additional resistance thereby reducing leakage current in path from supply to ground. In stacked LCNMOS technique, every transistor in the network is duplicated with both the transistors bearing half the original transistor width. It overcomes the limitation of sleep technique by retaining states. All the performances has been investigated using 90nm technology at one voltage and evaluated by the comparison of the simulation result obtained from T-SPICE