New Technique for Reducing Sub-threshold Leakage in SRAM

Abstract

Suppressing the leakage current in memories is critical in low-power design. Memory leakage suppression is critically important for the success of power-efficient designs, especially for ultra-low power applications. As the channel length of the MOSFET reduces, the leakage current in the SRAM increases. One method is to reduce the standby supply voltage (VDD) to its limit, which is the Data retention voltage (DRV), leakage power can be substantially reduced. This paper present a method based on controlling the leakage current by introducing the leakage controlled transistors in the SRAM. In the proposed model, we introduce two pairs of two leakage control transistors (a p-type and a n-type) within the SRAM cell for which the gate terminal of each leakage control transistor is controlled by the source of the other. This increases the resistance of the path from to ground, leading to decrease in leakage currents. The proposed SRAM cell cuts down the leakage current without increasing the dynamic power dissipation.