Submicron Channel Length Research Articles

Effect of source–drain contact and channel length on the performance of vertical thin-film transistors

Vertical thin-film transistors (V-TFTs) with an InSnO-stabilized ZnO channel were fabricated. The vertical architecture enables devices with submicron channel lengths (≤500 nm) to afford delivering drain current greatly exceeding that of conventional planar TFTs. Due to the submicron length of the V-TFT channel, an on/off state current higher than 107 can be achieved even with a drain voltage of 0.01 V, and the subthreshold swing was kept in the tens of mV/dec range owing to the efficacious device preparation. In order to understand the influence of structures on the device performance, the source–drain (S/D) contact and the channel length of V-TFTs were designed and studied. The results show that the increase in the contact area between the active layer and the S/D region can reduce the S/D contact resistance, thus affecting the drain current across the threshold region. When the channel length is shortened to a deep submicron size, the electrostatic coupling between the source and drain electrodes will lead to a decrease in the S/D barrier. This leads to the leakage-induced barrier reduction effect of V-TFTs.

Scaling carbon nanotube field effect transistors to 30 nm channel length on pretreated PET

With the extensive application of flexible circuits to artificial intelligence (AI) and the internet of things (IoT), high requirements have been promoted for the integration and miniaturization of flexible circuits. However, the vast majority of transistors on flexible substrates reported so far have micrometer-level channel length (Lch), seriously affecting the integration abilities of flexible circuits. In this work, we explore the scaling behaviors of flexible carbon nanotube field effect transistors (CNT FETs) by fabricating p-type flexible CNT FETs with Lch varying from 2 μm to 70 nm on polyethylene terephthalate (PET) substrates. The improved width-normalized on-state current (Ion/Wch), transconductance (gm) and near-constant gate efficiency indicate that CNTs have great potential in constructing ultra-small flexible FETs. Additionally, we fabricate a CNT FET with a 30-nm channel length on a cleaned PET substrate using a self-aligned top-gate structure; this CNT FET can achieve a high on-state performance of 103 μA/μm when Vds = −0.8 V. The pitch size of the device is 230 nm, which is the smallest size of flexible transistors so far. Even with deep submicron and nanometer channel lengths, the yields of flexible CNT FETs can reach 60% (33/56); which is benefiting from the pretreated substrate, demonstrating the potential for large-scale production.

Effect of Single Spinel Phase Crystallization on Drain-Induced-Barrier-Lowering in Submicron Length IZTO Thin-Film Transistors

This study shows the effect of single spinel phase crystallization on drain-induced barrier lowering (DIBL) of indium-zinc-tin-oxide (IZTO) thin-film transistors (TFTs) with submicron channel length. The 0.9-μm-long amorphous IZTO (a-IZTO) TFT shows a poor DIBL of 318 mV/V. In contrast, a significant improvement in the DIBL is achieved in the single spinel phase IZTO (s-IZTO) TFT, which could be attributed to the suppression of lateral diffusion of oxygen vacancy (VO) and low VO defects through crystallization-induced enforcement of metal-oxygen bonds. Consequently, 0.9-μm-long s-IZTO TFT reveals a small DIBL of 92 mV/V as well as a high field-effect mobility of 90.1 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /Vs and a low subthreshold swing of 0.1 V/dec. In addition, reliability against external bias temperature stress is considerably improved through single-phase crystallization, leading to an insignificant threshold voltage shift of +0.4 (–0.4) V under positive (negative) bias stress with electric field of 2 (–2) MV/cm at 60 °C for 10,000 s, respectively, in the 0.9-μm-long s-IZTO TFT.

48‐1: Invited Paper: Oxide Semiconductor Thin‐Film Transistors with Deep Submicron Channel Fabricated with Hyperlithography

We propose and present in detail the new method to enable the deep submicron channel length in oxide semiconductor thin‐film transistors with conventional lithographic tool in large‐area substrates. Up till now we succeeded in fabricating the oxide thin‐ film transistors with 60 nm channel length with the performance of ~300 µA/µm at a drain bias of 1.5 V, and gate bias of 2 V, ION/IOFF larger than 109, subthreshold swing of 100 mV/dec, and turn‐on voltage of about ‐0.47 V . We hope that our technique will contribute to open a new era as a backplane technology for transparent ultra‐high‐resolution displays such as hologram, AR, and/or XR.

Submicron Vertical Channel Organic Electrochemical Transistors with Ultrahigh Transconductance

AbstractOrganic electrochemical transistors (OECTs) belong to the class of electrolyte gated organic transistors (EGOTs) that offer a smooth interface with biology in combination with high transconductance values of typically a few mS. Fabrication‐wise, though, most of the up‐to‐date reported devices are limited to two dimensional structures, where the transistor channel is patterned on the same plane as the source and drain electrodes. Here, a method is introduced for the fabrication of integrated vertical channel OECTs (vOECTs) with submicron channel length. By employing electrodeposition, a vertical channel sandwiched between the source and drain electrodes is created. Channel lengths down to 60 nm are demonstrated, giving rise to ultrahigh transconductance of up to 275 mS. Accounting for the voltage loss on the device connection tracks, an intrinsic transconductance of vOECTs of 500 mS is found. The vOECTs are three‐dimensional transistors finding relevant application in “organ‐on‐a‐chip” and implantable devices, where high amplification and small footprint are demanded.

(Invited) Metal Oxide Thin-Film Transistors with Deep Submicron Channel Enabled By Self-Aligned Nano Gap Patterning

We demonstrate the fabrication technology of metal oxide semiconductor thin-film transistors (TFTs) with deep submicron channel length and their electrical characterization. We call the method as self-aligned nano gap patterning (SANP), where the pattern resolution is limited not by optical diffraction in photolithography, but by the details in etching and deposition process. Therefore, this makes it enable to overcome the obstacle in the scale down of large area electronic devices, for which high resolution photolithography tools such as VUV or XUV used in semiconductor industry are almost useless due to the extremely low throughput and high cost. In this work, we employ the contact aligner with line and space resolution of 3 μm, and the oxides TFTs with 0.1μm channel length was successfully fabricated with field-effect mobility of 12 cm2/Vs, subthreshold swing of 100 mV/dec, Ion/Ioff of 1010, and turn-on voltage of -0.88 V.

32‐4: Metal Oxide Thin‐Film Transistors with 0.1 μm channel length formed by Self‐Aligned Nanogap Patterning

We demonstrate the oxide semiconductor TFTs with submicron channel length realized by Self‐Aligned Nanogap Patterning (SANP) process which makes it enable to overcome the resolution limit of conventional photolithographic tool in the large area electronics. Using contact aligner with line and space resolution of 3 pm, the Al‐doped InZnSnO TFT with field‐effect mobility of 12 cm2/Vs, subthreshold swing of 100 mV/dec, Ion/IOff 1010, and turn‐on voltage of −0.88 V was successfully fabricated in the channel length of about 100 nm

Design of microwave β-(Al x Ga x )2O3/Ga2O3 lateral Schottky barrier diodes

High power microwave Schottky barrier diodes (SBDs) are required to develop detectors and mixers in advance the millimeter-wave (mm-wave) wireless technologies such as fifth generation long-term evolution. To achieve high efficiency and sensitivity in SBDs, materials/structures with high mobility and low series resistance are needed. In this regard, we have proposed the two dimensional electron gas of β-(Al x Ga)2O3/Ga2O3 heterostructure channel lateral SBDs (LSBDs) for the first time. To design high performance LSBDs, detailed physical models of both β-(Al x Ga)2O3 and Ga2O3 were studied and characterized with experimental results. These physical models were used to perform realistic numerical simulations of DC, small signal and large signal conditions. It was observed that the structural and compositional aspects of heterostructure are largely influencing the small signal sensitivity and cut-off frequencies. Also the large signal analysis reveals that the LSBD can operate in linear detection of microwave signals, up to 38 dBm. By scaling down the device to a sub-micron channel length, a cut-off frequency of 1.5 THz was achieved in the proposed LSBD. Comparison with state-of-the-art SBDs, the observations from DC, small signal and large signal analysis recommend the proposed β-(Al x Ga)2O3/Ga2O3 LSBDs for high power and mm-wave/sub-THz detector/mixer application.

Submicron Channel Length High-Performance Metal Oxide Thin-Film Transistors

In this work, we present a new fabrication methodology to enable high-performance thin-film transistor (TFT) with submicron channel length. The method can exceed the resolution limit of a conventional photolithography compatible with large-area substrates such as a glass or a plastic. The lift-off and back-channel etching techniques were employed to delineate the channel in the bottom-gate top-contact configuration. The Al-doped InZnSnO TFTs with 0.8 μm channel length were successfully fabricated. Field-effect mobility of over 50 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /Vs, subthreshold swing of 90 mV/dec, on/off current ratio of > 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">10</sup> , and turn-on voltage of -0.24 V were obtained. Considering the compatibility with the current manufacturing process and facility, we expect that the method can be incorporated in an easy and cost-effective way into the TFT array for high-performance large-area electronics.

9‐4: Fabrication of Oxide‐Semiconductor FETs with Submicron Channel Length

This work presents oxide‐semiconductor FETs with submicron channel length (L) below the resolution limit of the exposure system used in their fabrication on glass substrates. The improved patterning method proposed here enables FET fabrication with L = 0.7 μm and small variation in the characteristics, leading to high on‐state current.

Blue Laser Annealed Sub-Micron Channel P-Type Low Temperature Poly-Si TFT Without Kink Effect for High-Resolution Display

We report sub-micron channel length (0.5 μm), low-temperature polysilicon(LTPS) thin-film transistor (TFT) using blue laser annealing (BLA) for ultra-high-resolution displays. The TFTs exhibited negligible kink effect in output characteristics with excellent negative bias temperature stability. Protrusion-free BLA LTPS is evident from the transmission electron microscopy (TEM) image. Technology computer-aided design (TCAD) simulation reveals that the protruded LTPS with grain boundaries has ~1.4 times higher electric field than protrusion-free LTPS. This causes high impact generation rate of 3.76 x 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">14</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sup> s <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> (~8 times) compared to 4.64 x 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">13</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sup> s <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> for protrusion-free LTPS TFTs. It is demonstrated that protrusion-free LTPS can achieve kink-free, sub-micron short channel devices.

Computation of subthreshold slope in submicron HEMT with parasitic effects

The subthreshold slope of a submicron high-electron-mobility transistor (HEMT) is analytically computed as a function of vertical electric field for various parasitic effects and structural parameters. The simultaneous solution of Poisson’s equation and the carrier density equation provides drain current from which subthreshold slope is calculated subject to appropriate boundary conditions. Simulation is carried out at optimised channel length and applied bias for which maximum transconductance and higher differential conductance are already reported. Results show that for a particular range of gate-to-source bias, V GS, simulated findings match very closely to the ideal value of 60 mV/decade. The role of an aluminium nitride (AlN) buffer layer in tailoring the subthreshold slope magnitude is critical and the effect of submicron channel length, which is otherwise absent in conventional HEMTs, is explored. A combination of both the electric fields in realistic situations is investigated, the findings of which will play a key role in device application for wireless communication systems.

P‐1.5: Fabrication of Self‐Aligned Top‐Gate Amorphous InGaZnO Thin‐Film Transistors with Submicron Channel Length

A method based on photoresist trimming technique was developed to fabricate self‐aligned top‐gate amorphous indium‐gallium‐zinc oxide (a‐IGZO) thin‐film transistors (TFTs) with submicron channel length. In this scheme, a hard mask layer was adopted to further reduce the channel length defined by the photoresist trimming process. With this method, the self‐aligned top‐gate a‐IGZO TFT with channel length of about 0.6µm is fabricated. Moreover, the fabricated device shows a field effect mobility of 6.8 cm2/Vs, a subthreshold swing of 0.29V/decade, and high ON/OFF current ratio up to 108.

Top-Contact Self-Aligned Printing for High-Performance Carbon Nanotube Thin-Film Transistors with Sub-Micron Channel Length.

Semiconducting single-wall carbon nanotubes are ideal semiconductors for printed thin-film transistors due to their excellent electrical performance and intrinsic printability with solution-based deposition. However, limited by resolution and registration accuracy of current printing techniques, previously reported fully printed nanotube transistors had rather long channel lengths (>20 μm) and consequently low current-drive capabilities (<0.2 μA/μm). Here we report fully inkjet printed nanotube transistors with dramatically enhanced on-state current density of ∼4.5 μA/μm by downscaling the devices to a sub-micron channel length with top-contact self-aligned printing and employing high-capacitance ion gel as the gate dielectric. Also, the printed transistors exhibited a high on/off ratio of ∼105, low-voltage operation, and good mobility of ∼15.03 cm2 V-1s-1. These advantageous features of our printed transistors are very promising for future high-definition printed displays and sensing systems, low-power consumer electronics, and large-scale integration of printed electronics.

Performance evaluation of channel length downscaling of various high voltage AlGaN/GaN power HEMTs

Channel length downscaling characteristics of various lateral AlGaN/GaN high electron mobility transistors (HEMTs) are simulated. Quasi‐constant‐field scaled MOS channel HEMTs show superior performance over two‐dimensional electron gas (2DEG) channel HEMTs at deep submicron channel lengths. The adverse effects of deep submicron channel length on threshold voltage, drain‐induced barrier lowering, subthreshold swing, transconductance and on‐off current ratio are seen to be much less pronounced in MOS channel HEMTs compared with 2DEG channel HEMTs. Switching capabilities of enhancement mode HEMTs at different channel lengths are evaluated and compared using a new intrinsic maximum switching frequency (fm,IG) figure‐of‐merit.

Design Considerations for ZnO Transistors Made Using Spatial ALD

We have used spatial atomic layer deposition (SALD) to fabricate metal oxide thin-film devices with unusually simple processes. Selective area deposition allows us to fabricate transistors and circuits additively and with digital design variations when used in combination with an inkjet-printed inhibitor. In a second approach, we use the conformal nature of SALD films to produce self-aligned sub-micron channel length vertical transistors that have large alignment tolerances and are suitable for high-performance thin-film electronics. We discuss device design considerations for both architectures.

Design Considerations for ZnO Transistors Made Using Spatial ALD

We have used spatial atomic layer deposition (SALD) to fabricate a variety of thin film transistors using zinc oxide as the semiconductor and aluminum oxide as the insulator. The conductive electrodes are formed either from aluminum-doped zinc oxide, or from thermally evaporated metals. Spatial ALD can be performed at atmospheric pressure, and can grow coatings very quickly. Deposition occurs without a requirement for valve timing, by moving the substrate relative to the precursors flowing from a coating head. The proximity of the substrate to the coating head is controlled via a gas bearing design – allowing SALD to operate with purge times that are equivalent to the precursor exposure times (sub-second) unlike traditional chamber-based systems. In this talk we will discuss examples of thin film electronics with architectures that are enabled by ALD, with a particular focus on spatial ALD. We use the well known conformality of ALD to build self-aligned, sub-micron channel length, vertical transistors. The vertical transistor electrical performance is impressive compared to amorphous silicon TFTs, for example, yet the alignment tolerances inherent in the fabrication process are large.Our second approach to fabricating devices uses selective area deposition, with inkjet-printed inhibitor, to pattern all the active layers. We build full transistors and circuits using one inhibitor ink, the SALD system, and an oxygen plasma to clean the substrate. Performance of the resulting transistors and circuits match photolithographically patterned ones.

Submicron organic thin-film transistors fabricated by film profile engineering method

In this work, we explore and demonstrate the feasibility of a film profile engineering (FPE) concept in fabricating pentacene-based organic thin-film transistors (OTFTs) with submicron channel length. The FPE scheme utilizes a suspended bridge built on the wafer and the specific deposition conditions to form thin films with desirable profiles. In order to form a continuous pentacene channel under the bridge, the background pressure of thermal evaporator is adjusted by pumping down the filling N2 to a specific level. The results show that, by setting the deposition pressure at 3 mtorr, functional operations of OTFTs with channel length ranging from 0.4 to 0.6 μm are obtained.

Organic thin film transistors and polymer light-emitting diodes patterned by polymer inking and stamping

To fully realize the advantages of organic flexible electronics, patterning is very important. In this paper we show that a purely additive patterning technique, termed polymer inking and stamping, can be used to pattern conductive polymer PEDOT and fabricate sub-micron channel length organic thin film transistors. In addition, we applied the technique to transfer a stack of metal/conjugated polymer in one step and fabricated working polymer light-emitting devices. Based on the polymer inking and stamping technique, a roll-to-roll printing for high throughput fabrication has been demonstrated. We investigated and explained the mechanism of this process based on the interfacial energy consideration and by using the finite element analysis. This technique can be further extended to transfer more complex stacked layer structures, which may benefit the research on patterning on flexible substrates.

Crossover from diffusive to quasi-ballistic transport

We present a detailed study of quasi-ballistic transport in submicron semiconductor channels. The electron distribution in such channels differs significantly from a near-equilibrium, shifted Maxwell-Boltzmann distribution function, and displays a large broadening, as well as pronounced features, peaks and shoulders, in the high-velocity tail of the distribution associated with the nonequilibrium and quasi-ballistic nature of the electron transport. For submicron channel lengths, analyses of the spatial dependence of the velocity distribution function show that scattering in the entire channel is important and that the scattering efficiency has a strong spatial dependence. In this article, we particularly study the crossover between the diffusive and quasi-ballistic regimes of transport and find characteristic signatures in (i) the electrostatics, which manifests as a redistribution of the voltage drop from the channel to the contact regions; (ii) the electron density, where exponential and linear spatial dependences of the source-injected and channel- and drain-backscattered electron densities are signatures of diffusive and quasi-ballistic transport, respectively, and (iii) the electron distribution function, where the source-injected ballistic peak observed in the quasi-ballistic regime disappears at the onset of diffusive transport.