Submicron Channel Length Research Articles

Megahertz operation of organic field-effect transistors based on poly(3-hexylthiopene)

Switching speed is crucial for many applications in organic electronics. The possibility to achieve higher frequencies will enable new fields of applications. The authors demonstrate high-frequency organic thin film transistors based on poly(3-hexylthiophene). Transistors with submicron channel lengths show unity-gain bandwidth of 2MHz in air at low supply voltages of 10V. For channel lengths L below 500nm deviations from ideal L scaling law are observed experimentally, which are attributed to contact effects. They present a model beyond the ideal scaling law to predict the maximum operational frequency based on transistor parameters, geometry, and contact resistance.

Characterization of functionalized pentacene field-effect transistors and its logic gate application

Functionalized pentacene, 6,13-bis(tri-isopropylsilylethynyl)pentacene (TIPS-pentacene), field-effect transistors (FETs) were made by both thermal evaporation and solution deposition methods, and the mobility was measured as a function of temperature and intensity of incident illumination. The field-effect mobility (μFET) has a gate-voltage dependent activation energy. A nonmonotonic temperature dependence was observed at high gate voltage (VG<−30V) with an activation energy of Ea∼60–170meV, depending on the fabrication procedure. The gate-voltage dependent mobility and nonmonotonic temperature dependence indicate that shallow traps play important role in the transport of TIPS-pentacene films. The current in the saturation regime as well as the mobility increase upon light illumination in proportion to the light intensity, mainly due to the photoconductive response. Transistors with submicron channel length showed unsaturating current-voltage characteristics due to the short channel effect. Realization of simple circuits such as NOT (inverter), NOR, and NAND logic gates are demonstrated for thin film TIPS-pentacene transistors.

Numerical study on the scaling of a-Si:H thin film transistors

In this article we discuss the impact of channel length scaling on the above threshold current characteristics of hydrogenated amorphous silicon (a-Si:H) thin film transistors (TFTs). MEDICI simulation results of the interface surface potential show a lowering of the potential barrier for shorter channel lengths. This suggests a decrease in threshold voltage and increase in subthreshold slope with drain voltage particularly in submicron channel lengths, causing a nonsaturating output current. Simulation results of the above threshold current-voltage characteristics for short channel TFTs corroborate with measurement data of fabricated devices.

Low-cost fabrication of submicron all polymer field effect transistors

All polymer field effect transistors have been fabricated combining nanoimprint lithography and inkjet printing. Trenches with hydrophilic bottoms confined by hydrophobic walls with considerable height are patterned by nanoimprint lithography. Conducting polymer solutions were then delivered into these trench liquid containers by inkjet printing. Dried conducting polymer in nearby trenches forms source-drain electrodes with the channel length accurately defined by the gap in between the designed two trenches. Top-gate all polymer field effect transistors with submicron channel lengths were successfully realized by such low-cost process.

Short-channel polymer field-effect-transistor fabrication using spin-coating-induced edge template and ink-jet printing

A method to fabricate polymer field-effect transistors with submicron channel lengths is described. A thin polymer film is spin coated on a prepatterned resist with a low resolution to create a thickness contrast in the overcoated polymer layer. After plasma and solvent etching, a submicron-sized line structure, which templates the contour of the prepattern, is obtained. A further lift-off process is applied to define source-drain electrodes of transistors. With a combination of ink-jet printing, transistors with channel length down to 400 nm have been fabricated by this method. We show that drive current density increases as expected, while the on/off current ratio 106 is achieved.

Ambipolar injection in a submicron-channel light-emitting tetracene transistor with distinct source and drain contacts

We report on organic light-emitting transistors with a submicron-channel length, gold source, and calcium drain contacts. The respective contact metals allow efficient injection of holes and electrons in the tetracene channel material. Transistor characteristics were measured in parallel with electroluminescence being recorded by a digital camera focused on the transistor channel. In the case of submicron-channel lengths, the transistor source-drain current at higher gate voltages was determined by the source-drain voltage. At larger channel lengths, the source-drain current was limited by the injection of electrons from the calcium contact, as hole ejection to this contact was fully blocked. The hole blocking is explained in terms of a chemical reaction occurring at the Ca/tetracene interface.

Study of asymmetrical effects of silicon submicron transistors

We studied the asymmetrical effect of submicron channel length NMOS silicon transistors. The threshold voltage of transistor was determined by transconductance (gm) extraction method and constant-current (CC) method. The effective channel length (Leff) was determined by ‘shift and ratio’ methods. The short channel and reverse short channel effect were observed from the threshold voltage (Vto) versus channel width (W) curve. The I–V curves were not shown significant asymmetry of drain and source. The results showed that the asymmetry of drain and source increased with reducing the channel length. The standard deviation of threshold voltage and effective channel length were increased with decreasing channel length.

Analytical Drain Thermal Noise Current Model Valid for Deep Submicron MOSFETs

In this paper, a physics-based MOSFET drain thermal noise current model valid for deep submicron channel lengths was derived and verified with experiments. It is found that the well-known /spl mu/Q/sub inv//L/sup 2/ formula, previously derived for long channels, remains valid for short channels. Carrier heating in the gradual channel region was taken into account implicitly with the form of diffusion noise source and then impedance field method taking velocity saturation effect was used to calculate the external drain thermal noise current. The derived model was verified by experimental noise for devices with channel lengths down to 0.18 /spl mu/m. Excellent agreement between measured and modeled drain thermal noise was obtained for the entire V/sub GS/ and V/sub DS/ bias regions.

Performance and Degradation in Single Grain-size Pentacene Thin-Film Transistors

Submicron channel-length pentacene thin-film transistors (TFTs) were fabricated by electron beam lithography and a lift-off process. It was found that pentacene TFTs operated in the submicron channel length, but an enhancement of the off-stage leakage current and a large hysteresis were observed. By further investigation, we found that the large hysteresis observed in the submicron channel length was due to the moisture in the air. We also found a non-moisture-related degradation, in addition to a moisture-related one, by a time-dependent degradation measurement. It is of great importance both to avoid the moisture invasion and to reduce charging sites in the channel for reliable pentacene TFTs.

SiGe(C) epitaxial technologies—issues and prospectives

Epitaxial layers of SiGe(C) have entered mainstream Si processing—forming base regions in heterojunction bipolar transistors. There are also exciting prospects that SiGe(C) could impact MOS technologies. In both cases heteroepitaxial layers enable very significant performance enhancements at device and circuit level. A related area and a familiar hot-potato is silicon epitaxy for device active regions in MOS technologies—where tightly controlled doping distributions can be incorporated to facilitate device function at deep submicron channel lengths. CVD is a preferred epitaxy deposition technique for production—currently LP-CVD and UHV-CVD dominate. Each of these techniques demand much of the technology and have their respective strengths and weaknesses. Issues regarding matrix and doping control, uniformity, blanket and selective area growth and throughput (a sensitive area) will be addressed. Also in the CVD portfolio is LEPE-CVD—a recent contender for the production arena which has the facility of being able to access very high deposition rates as required for example in depositing relaxed buffer layer material required as ‘virtual substrates’ for higher Ge content layers. SS-MBE, traditionally the favourite technique for research, also has distinct possibilities for development as a production tool. Here the issues relate primarily to throughput and system design, and (surprisingly) matrix profile control. These techniques will be outlined and reviewed along with issues which determine their development as the competition hots up in epitaxy, and as more complex and high Ge content structures are needed to progress Si technology to new performance heights and application areas.

Low-frequency noise in deep-submicron metal–oxide–semiconductor field-effect transistors

The author reviews the recent results obtained on the low-frequency noise characteristics of deep-submicron metal–oxide–semiconductor field-effect transistors (MOSFETs). The manuscript covers measurements, analysis and modelling of 1/f noise as well as random telegraph signals (RTS). In addition, techniques are presented where RTS and 1/f noise measurements can be utilised to characterise the oxide traps responsible for these fluctuations, namely the position of the trap in the oxide and along the conduction channel, the trap energy, and the associated screened scattering coefficient. Most of the analysis is based on the classical three-dimensional treatment of charge carrier calculation, although a section is reserved for charge quantisation and its effect on RTS. For noise modelling, an improved physics-based 1/f noise model is presented where the Berkeley short channel IGFET model (BSIM3) has been modified to include the threshold variation along the channel. This model merges into the classical BSIM3 for supermicron devices. The noise models presented in the manuscript are based on data that were obtained on many submicron channel length n- and p- MOSFETs made by different leading manufacturers using different technologies. It is expected that the developed models will be valid for all advanced MOSFETs.

A new unified model for submicron MOSFETs

A new unified analytical model for submicron MOSFETs, valid for all regions of operation (including deep subthreshold), is presented in this paper. It accounts for the changes in the subthreshold slope with respect to the applied drain voltage. A new unification technique is proposed, which preserves the continuity of the drain current and its derivatives with respect to the applied terminal voltages at the various operating region boundaries. It passes the benchmark tests of Tsividis and Suyama (IEEE J. Sol. St. Circ., 29 (1994) 210–216) adequately, and thus, is suitable for analog circuit computer-aided design work. Also, the simulated results match well with the experimental results for deep submicron channel length devices.

30.4: Short‐Channel Effect of Sub‐Micron Poly‐Si TFTs with Large Poly‐Si Grains

AbstractTo study 3 V‐driven LSI‐like TFTs, we fabricated high‐temperature n‐channel poly‐Si TFTs, some of which had a subthreshold slope of 90 mV/dec and an electron field mobility of 432 cm2/Vs, with submicron channel length and large poly‐Si grains. We only observed an anomalous parasitic bipolar transistor effect in the TFTs with good trans‐conductance, and concluded that the grain‐boundary affects the trans‐conductance severely than the threshold voltage and the subthreshold slope.

Monte Carlo Simulation of a Submicron MOSFETIncluding Inversion Layer Quantization

A Monte Carlo simulator of the electron dynamics in the channel, coupled with a solution of the two‐dimensional Poisson equation including inversion‐layer quantization and drift‐diffusion equations has been developed. This simulator has been applied to the study of electron transport in normal operation conditions for different submicron channel length devices. Some interesting non‐local effects such as electron velocity overshoot can be observed.

New understanding of LDD NMOS hot-carrier degradation and device lifetime at cryogenic temperatures

This work shows that the worst-case gate voltage stress condition for LDD nMOSFETs is a strong function of the channel length, drain voltage, and operating temperature. A new cross-over behavior of the worst-case gate voltage condition is reported at low temperatures. New understanding of the hot-carrier mechanisms at low temperatures is also discussed. Low temperature effects such as freeze-out are shown to have important contributions to the hot-carrier behavior at low temperatures. A trend is identified for the first time which suggests important consequences for the hot-carrier reliability of deep sub-micron channel length MOSFETs under normal operating temperatures.

Sub-micron strained Si:SiGe heterostructure MOSFETs

Si:SiGe heteroepitaxy raises the prospect of combining the attributes of high mobility channel engineering with mainstream stricon MOS technology. The design of the heteroepitaxial structure is investigated here by means of a response surface methodology study of strained SiGe p-channel heterostructure MOSFETs using two-dimensional numerical device simulation. The reduced effective density of states inherent in a strained channel layer is included and shown to result in a lower inversion charge concentration in the channel. Particular performance metrics evaluated are the gate bias range for buried channel operation and the maximum channel charge, which determines the peak transconductance ( g m) and maximum current drive. It is shown that at the high levels of sub-channel doping appropriate for MOSFETs with sub-micron channel lengths, a small or non-existent window of buried channel operation may arise due to the onset of parasitic surface inversion. Various means of increasing the contribution of strained channel conduction to the drain current are considered, including composition grading and modulation doping. The conclusions are equally applicable to strained silicon n-channel heterostructure MOSFETs.

Theoretical analysis and modeling of submicron channel length DMOS transistors

Previous analytical models of the DMOS transistor are inadequate at the shorter gate lengths, and can lead to spurious predictions of DMOS device behavior. To avoid such shortcomings, an improved DMOS model is proposed to better address DMOS performance issues. These include the identification of desirable device operating regimes and the examination of device frequency response. Increases in DMOS gate capacitance, which have previously been demonstrated only by computer simulation and device measurements, are now modeled analytically. Furthermore, in demonstrating the shortcomings of previous DMOS models, a universal condition for current saturation in MOS devices is derived. The derivation and applicability of the universal condition is independent of mobility model.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Impact of distributed gate resistance on the performance of MOS devices

This paper describes the impact of gate resistance on cut-off frequency (f/sub T/), maximum frequency of oscillation (f/sub max/), thermal noise, and time response of wide MOS devices with deep submicron channel lengths. The value of f/sub T/ is proven to be independent of gate resistance even for distributed structures. An exact relation for f/sub max/ is derived and it is shown that, to predict f/sub max/, thermal noise, and time response, the distributed gate resistance can be divided by a factor of 3 and lumped into a single resistor in series with the gate terminal. >

Influence of statistical dopant fluctuations on MOS transistors with deep submicron channel lengths

The influence of statistical doping fluctuations on the threshold voltage of a MOS transistor is examined. It is found that for transistors with a channel area of less than 0.1μm 2 (corresponding to a channel length of 0.1μm with a W/L ratio of 10) statistical doping fluctuations will result in significant fluctuations of the threshold voltage.

Simulation and fabrication of submicron channel length DMOS transistors for analog applications

The use of an asymmetric MOS structure for superior analog circuit performance is considered. Results from the fabrication of 1- mu m-gate length DMOS transistors show increases of up to 1.9 in transconductance, 10 in output resistance, and 8 in intrinsic gain when compared to NMOS structures of similar gate length and threshold voltage. Substrate current is also reduced by up to a factor of 10. This represents the first reported results of submicron channel length DMOS transistors. The standard 7 degrees implantation angle has significant impact on DMOS fabrication and is shown to produce a usable asymmetric DMOS from an otherwise symmetric DMOS. An optimal implant energy and diffusion time are shown to exist for DMOS enhancement region formation. Two-dimensional process and device simulators have proved necessary to develop the DMOS process, as well as to qualitatively explain body effect reduction and threshold voltage determination. The DMOS process has successfully yielded experimental circuits including a single ended operational amplifier of folded cascode technology and a 101-state ring oscillator. >