Stress In Solder Joints Research Articles

Interfacial thermal stresses in solder joints of leadless chip resistors

A novel two-dimensional analytical model has been developed for the interfacial thermal stresses in the solder joints of a leadless chip resistor (LCR) assembly under both plane stress and plane strain conditions. Both global and local expansivity mismatches are incorporated into the model. Interfacial thermal stresses are approximated using elementary strength of materials theory. Governing differential equations are linearized through a finite difference discretization procedure. The conditions of zero shear stress at the free edges and self-equilibrated peel stresses are met. The model is more accurate than existing ones, is mathematically straightforward, and can be extended to include inelastic behavior. The results are compared with available data in the literature and finite element analysis, and a geometry optimization is performed for a sample LCR as an example of the use of the model.

Parametric study on flip chip package with lead-free solder joints by using the probabilistic designing approach

The low cost tin–lead solders have been widely used in electronic industries for many years, but it is also well known to be one of the major factors for environmental pollution risk. Today, several kinds of lead-free soldered alloy have been developed as a choice for replacement of the high lead solders. However, because of the shortage of the facilitated experiment data for the thermal mechanical kinetics characterisations of these alloy, only very few parts of the parametric influence on reliability of the lead-free soldered flip chip package have been realized. In order to launch a further investigation on this issue, a numerical simulation-based parametric study on a flip chip is implemented in this paper by using the probabilistic designing approach. It combines the response surface strategy and the Monte Carlo random simulation method. The peak values of the inelastic strain and hydrostatic stress in solder joints, as well as the peel stress and the shear stress in the interface between silicon and underfill are investigated and used as response parameters. The response surface approximate functions between the output stress/strain values and the major packaging parameters are produced in the design of experiment (DOE) procedure of the numerical simulations. Statistical results of the parametric influence on lead-free soldered flip chip are also acquired by the Monte Carlo random simulation process. The results of our studies have shown that the different packaging parameters will influence the output stress/strain state of the lead-free soldered flip chip package in a very different way and degree. It is indicated that the substrate thickness is a major factor that should be taken into account for the lead-free package optimization design.

Damage accumulation under repeated reverse stressing of Sn-Ag solder joints

To better understand the effect of repeated reverse stress in solder joints, a new testing method was developed. Tin-silver solder joints were fabricated, constrained between Cu blocks, and then subjected to repeated shear loading in a tensile tester. Constant strain amplitudes were applied to simulate service conditions. However, large loads were used to accelerate the damage accumulation. Microstructural features of the damage were very similar to those found with studies on thermomechanical fatigue (TMF) of small, single shear lap samples. Concentrated-shear banding or striations were observed to form along Sn dendrites. The load behavior of the solder with each cycle and during hold times at the extreme strain amplitude was consistent with damage accumulating with each successive cycle. Effects of strain amplitude, hold times at the stress extremes, number of cycles, and solder-joint thickness were found to play significant roles on the stress-strain behavior and surface damage.

Effect of substrate flexibility on solder joint reliability

Solder joint fatigue failure is a serious reliability concern in area array technologies, such as flip chip and ball grid array packages of integrated-circuit chips. The selection of different substrate materials could affect solder joint thermal fatigue lifetime significantly. The reliability of solder joint in flip chip assembly for both rigid and compliant substrates was evaluated by accelerated temperature cycling test. Experimental results strongly showed that the thermal fatigue lifetime of solder joints in flip chip on flex assembly was much improved over that in flip chip on rigid substrate assembly. Debonding area of solder joints in flip chip on rigid board and flip chip on flex assemblies were investigated, and it was found that flex substrate could slow down solder joint crack propagation rate. The mechanism of substrate flexibility on improving solder joint thermal fatigue was investigated by thermal mechanical analysis (TMA) technique. TMA results showed that flex substrate buckles or bends during temperature cycling and this phenomenon was discussed from the point of view of mechanics of the flip chip assembly during temperature cycling process. It was indicated that the thermal strain and stress in solder joints could be reduced by flex buckling or bending and flex substrates could dissipate energy that otherwise would be absorbed by solder joints. It was concluded that substrate flexibility has a great effect on solder joint reliability and the reliability improvement was attributed to flex buckling or bending during temperature cycling.

830 リフロープロセスの影響を考慮した電子パッケージはんだ接合部信頼性予測

It is concerned that residual stresses of solder joints in package assembly process are small because of solder joint stress relaxation. However, lead free solders are developed and applied to electronic devices today. It is uncertain that we can neglect solder joints residual stresses in lead free assembly process. Therefore, authors consider effects of package assembly process (reflow process) for solder joint reliability by using FEM analysis.

Effect of the drop impact on BGA/CSP package reliability

In this study, ball grid arrays (BGAs) and chip size packages (CSPs) were evaluated with respect to their solder joint reliabilities under drop impacts. The correlation between solder joint stresses and motherboard strains was confirmed by numerical analysis, and the motherboard strains caused by the drop impacts were measured to evaluate the BGA/CSP reliability. The authors found that the stress at a solder joint differs depending on the package structure, even if the motherboard strain is the same, and that underfilling eases the motherboard strain and disperses the stress concentrated on a solder joint.

Elastic, elastic‐plastic and creep analyses of wafer level chip scale package solder joints on microvia build‐up printed circuit boards

The solder‐joint reliability of solder‐bumped wafer level chip scale package (WLCSP) on microvia build‐up printed circuit board (PCB) subjected to thermal cycling conditions is investigated in this study. The 62Sn36Pb2Ag solder joints are assumed to be: an elastic material; an elastic‐plastic material; and a creep material which obey the Garofalo‐Arrhenius steady‐state creep constitutive law. The stress and strain in the corner solder joint of the WLCSP assembly are presented and compared for these three material models. Also, the results presented herein will be compared with that from creep analysis of the WLCSP on PCB without microvia build‐up layer.

Thermal cycling analysis of flip-chip solder joint reliability

The reliability concern in flip-chip-on-board (FCOB) technology is the high thermal mismatch deformation between the silicon die and the printed circuit board that results in large solder joint stresses and strains causing fatigue failure. Accelerated thermal cycling (ATC) test is one of the reliability tests performed to evaluate the fatigue strength of the solder interconnects. Finite element analysis (FEA) was employed to simulate thermal cycling loading for solder joint reliability in electronic assemblies. This study investigates different methods of implementing thermal cycling analysis, namely using the "dwell creep" and "full creep" methods based on a phenomenological approach to modeling time independent plastic and time dependent creep deformations. There are significant differences between the "dwell creep" and "full creep" analysis results for the flip chip solder joint strain responses and the predicted fatigue life. Comparison was made with a rate dependent viscoplastic analysis approach. Investigations on thermal cycling analysis of the temperature range, (/spl Delta/T) effects on the predicted fatigue lives of solder joints are reported.

The effects of underfill on the reliability of flip chip solder joints

Thermal fatigue damage of flip chip solder joints is a serious reliability concern, although it usually remains tolerable with the flip chip connections (of smaller chips) to ceramic boards as practiced by IBM for over a quarter century. However, the recent trend in microelectronics packaging towards bonding large chips or ceramic modules to organic boards means a larger differential thermal expansion mismatch between the board and the chip or ceramic module. To reduce the thermal stresses and strains at solder joints, a polymer underfill is customarily added to fill the cavity between the chip or module and the organic board. This procedure has typically at least resulted in an increase of the thermal fatigue life by a factor of 10, as compared to the non-underfilled case. In this contribution, we first discuss the effects of the underfill to reduce solder joint stresses and strains, as well as underfill effects on fatigue crack propagation based on a finite element analysis. Secondly, we probe the question of the importance of the effects of underfill defects, particularly that of its delamination from the chip side, on the effectiveness of the underfill to increase thermal fatigue life. Finally, we review recent experimental evidence from thermal cycling of actual flip chip modules which appears to support the predictions of our model.

ANALYSIS OF UNDERFILL ENCAPSULATION CURING DEFORMATIONS ON FLIP CHIP ON BOARD (FCOB) PACKAGE RELIABILITY

Finite element stress analysis was carried out to study the residual bending stresses in a Flip Chip On Board (FCOB) package assembly during the underfill encapsulation curing process. Out-of-plane warpage is generated in the package resulting from mismatches in the coefficients of thermal expansion (CTE) of the various materials in the assembly. In this paper, finite element analyses were conducted on 2-D plane-strain and 3-D models of the FCOB assembly to investigate the development of curing-induced bending stresses in the silicon die for a FCOB package. The FEA results for the die bending stresses were correlated to simple beam and plate bending theory with reasonable accuracy. Further FEA studies were conducted on the effect of underfill encapsulant material properties on the solder joint shear stresses. Elasto-plastic and creep analysis of the solder joints in the FCOB package subjected to a liquid-to-liquid thermal shock test condition provided useful data on the solder joint stress and strain response.

A Nonlinear Multi-Domain Thermomechanical Stress Analysis Method for Surface-Mount Solder Joints—Part II: Viscoplastic Analysis

This is part II of a two-part paper presented by the authors for thermomechanical stress analysis of surface mount interconnects. A generalized multi-domain Rayleigh Ritz (MDRR) stress analysis technique has been developed to obtain the stress and strain fields in surface-mount solder joints under cyclic thermal loading conditions. The methodology was first proposed in Part I by the authors and results were presented for elastic-plastic loading (Ling et al., 1996). This paper extends the analysis for viscoplastic material properties. The solder joint domain is discretized selectively into colonies of nested sub-domains at locations where high stress concentrations are expected. Potential energy stored in the solder domain and in the attached lead and Printed Wiring Board (PWB) is calculated based on an assumed displacement field. Minimization of this potential energy provides a unique solution for the displacement field, consequently, stress and strain distribution. The MDRR technique was demonstrated to provide reasonable accuracy for elastic deformation (Ling and Dasgupta, 1995) and for time-independent elastic-plastic deformation (Ling and Dasgupta, 1996) for solder joints under cyclic thermal loading conditions. A piecewise linear incremental loading technique is used to solve the nonlinear elastic-plastic problem. The focus in the current paper is primarily on time-dependent viscoplastic deformation of the solder joints. Full field elastic, plastic, and viscoplastic analyses are performed, and the stress, strain hysteresis loops are obtained. Results are presented for a J-lead solder joint as an illustrative example.

Stress Analysis of Surface-Mount Interconnections Due to Vibrational Loading

Recently, accelerated testing of surface mount interconnects under combined temperature and vibration environments has been recognized to be a necessary activity to ensure enhanced test-time compression. Successful use of vibration stresses requires a clear understanding of the correlation between vibrational damage and thermomechanical damage in surface mount solder joints. Hence, fatigue due to vibrational loading is important and accurate quantitative models are required to model effects due to vibrational fatigue. The proposed analysis in this paper contributes towards development of such quantitative models. This paper presents an approximate method to analyze stresses in surface mount solder joints subjected to vibration loading, using a generalized multidomain Rayleigh-Ritz approach (Ling and Dasgupta, 1995). The advantage of this approach is in its computational efficiency, compared to general-purpose finite element methods. Ling developed this approach in the context of thermomechanical stress analysis of solder joints. In this paper, the technique is modified and adapted for analyzing stresses caused by out-of-plane flexural dynamic modes of the printed wiring boards (PWBs). The analysis uses a two-step procedure where the local PWB curvatures are first estimated and the resulting deformations in the solder interconnect are then determined. The input boundary conditions for the first step are the bending moments in the PWB due to random vibrations. The stiffness of the interconnect assembly is then predicted using an energy method and curved-beam analysis. The bending moment and the computed stiffness of the interconnect assembly are then used to predict the local curvature of the PWB under any given surface-mount component by using an eigenfunction technique developed by Suhir (Suhir, 1988). In the second step of the analysis, the local curvature of the PWB is used as a boundary condition to predict the state of deformations, stresses, and strains in the solder joint using a modified version of the multidomain Rayleigh-Ritz approach. The overall method is applied to a specific example (J-lead solder joint) for illustrative purposes, and compared to finite element predictions for validation.

A Nonlinear Multi-Domain Stress Analysis Method for Surface-Mount Solder Joints

Solder joint fatigue failures are a potential reliability hazard in surface-mount electronic packages under cyclic thermal loading environment. Proper design and reliability assessment are thus crucial to ensure the fatigue endurance of the electronic packages. Accurate modeling of the stress and strain fields within the solder joint under cyclic thermal loading condition is of extreme importance since ultimately, a reasonable fatigue life estimation depends not only on a appropriate fatigue model, but more fundamentally, on accurately predicted stress and strain fields. Modeling stress and strain fields in solder joint in surface-mount electronic packages have never been an easy task since solder undergoes elastic, plastic and time dependent creep during each loading and unloading cycle. Some of the existing closed-form stress analysis models tend to oversimplify this complicated viscoplastic stress state, thus failing to give a reasonable prediction of the solder joint fatigue endurance. Extensive finite element analyses require prohibitive investment in terms of the analysis time and analyst expertise, especially when full scale elastic, plastic and creep analyses are performed. A generalized multi-domain approach proposed earlier by the authors is further developed in this paper to obtain the stress and strain fields in J-leaded surface-mount solder joint undergoing elastic-plastic deformation, under cyclic thermal environment (Ling et al., 1995). The Rayleigh-Ritz energy method based on a multi-field displacement assumption is used. In a previous paper (Ling et al., 1995), the results for analysis within elastic region had been demonstrated and were proved to be in agreement with finite element analysis. In this paper we further develop the methodology into plastic deformation region. Hysteresis loops for both the global and the local CTE mismatch problem can finally be generated. Results for two-dimensional elastic-plastic analysis are presented in the current paper. Creep deformation can be further modeled with this scheme by using time-stepping incremental techniques, and will be presented in a future paper. The final goal of this research is to predict the stress, strain and energy density distributions in the solder joint with reasonable accuracy. The fatigue assessment of the solder joint can then be performed by combining results from this stress analysis model with an appropriate damage model, for example, the energy-partitioning fatigue model (Dasgupta et al., 1992).

Design of 0.35-mm pitch QFP lead and its assembly technology

The solder joint reliability of a 0.35-mm lead pitch, 42-mm wide/spl times/42-mm long/spl times/23-mm high, 396 pin, ceramic quad flat package (QFP) was studied in terms of: 1) finite element analysis simulation; and 2) temperature cycling tests between -65/spl deg/C and +125/spl deg/C. Using the study results, physical design of the QFP leads, in terms of thickness, standoff, and Au surface finish were optimized. If the von Mises stress of a QFP solder joint can be optimized to be no more 16.7 kilogram square millimeter, we can guarantee QFP solder joint reliability over requested design life. Also, we developed a thermocompression (T/C) soldering process for the QFP. >

Elastic Analysis of Flip-Chip Solder Joints Undergoing Thermal Excursions

An elastic analysis is developed to provide estimates of the stresses in area array solder joints during thermal excursions. The analysis provides a rapid quantitative evaluation of the important stresses during elastic deformation, and may serve as a basis for the qualitative understanding of the loading of interconnects during thermal and power cycles.

The influence of dwell time on reliability of SMT solder joints under thermal cycling

The influence of dwell time on mechanical behaviour and fatigue life of SMT solder joints under thermal cycling has been investigated. The dwell time has two effects on the mechanical behaviour of SMT solder joints under thermal cycling: first, in the dwell time of high-temperature part, the stress in SMT solder joints will notably relax, and secondly, as the dwell time increase, the stress in solder joints in the low-temperature part of thermal cycling increases. With the increase of dwell time, the life of SMT solder joints under thermal cycling exponentially decreases.

Stress Relief in Solder Joints Due to the Application of a Flex Circuit

A stress analysis model is developed to assess the stresses in solder joints caused by thermal contraction mismatch between a low expansion flex-circuit (FC) and a high expansion rigid substrate. It is shown that application of low expansion FCs can result in significant stress relief for solder joints. This is due to the fact that the force acting on a joint cannot exceed the buckling force for the adjacent portion of the FC. It is shown that the strains in solder joints interconnecting FCs to rigid substrates can be made very small, thereby resulting in a substantially longer fatigue life of the interconnection. In the executed example these strains are about two orders of magnitude smaller, than in the case of a rigid board. The obtained results can be utilized as guidance in physical design of assemblies with FCs.

Mechanical Behavior of Flip-Chip Encapsulants

Requirements for the mechanical properties of the encapsulation material in a flip-chip design to prevent the solder and the encapsulation material itself from failure are presented on the basis of the developed analytical stress models, enabling one to predict the stresses caused by the expansion (contraction) mismatch of these materials. We evaluate and discuss the mechanical behavior of encapsulants for two encapsulation technologies: 1) encapsulant fills in the entire underchip space (silicone gels, epoxies); 2) encapsulant conformably coats the underchip surfaces (polyxylylene, polyimide). The calculations are carried out for an Advanced VLSI Package Design. The calculated data have indicated that low modulus silicone gel results in the lowest stresses. Polyxylylene should be considered as the second preference. Polyimide is also acceptable. Epoxies, however, could result in significant stresses in solder joints and therefore are less attractive. The final selection of the most feasible encapsulant should be done, of course, with consideration of all the electrical, chemical, and technological requirements.

Axisymmetric Elastic Deformations of a Finite Circular Cylinder With Application to Low Temperature Strains and Stresses in Solder Joints

We consider an axially symmetric elastic problem for a finite circular cylinder whose end planes are subjected to identical radial deformations. The obtained solution is used to evaluate low temperature strains and stresses for solder joints in assemblies having matched thermal expansion coefficients of the components. The thermomechanical behavior of solder joints is determined in this case by the mismatch between the solder and the soldered materials. It is shown that the arising strains and stresses, especially in the axial direction, can be rather great and could possibly result in the failure of the joint. They can be brought down by increasing its height-to-diameter ratio. The stresses can also be reduced if low modulus solder materials, such as 95 percent Pb/5 percent Sn solders or indium-based alloys, are used.

Surface Mount Technology (SMT) Substrate Material Requirements - A Brief Review

ABSTRACTThe state of the art for the printed circuit (pc) industry is the Surface Mount Technology (SMT) using leadless ceramic chip carriers (LCCCs). The SMT technique is used to design, fabricate, and assemble affordable high-speed, high-density electronic modules with reduced size and weight. However, to take full advantage of the SMT, new high-performance printed circuit board (PCB) substrate materials must be developed, especially if the goal is to satisfy the high reliability required in military applications. The most critical requirement is matching the in-plane coefficient of thermal expansion (CTE) with the SMT-PCB's and the chip carriers (LCCCs) to reduce the solderjoint stresses during thermal cycling. Solder-joint reliability can be improved significantly by tailoring the in-plane CTE to approximately 6–7 ppm/°C (of the alumina chip carrier) using Kevlar and/or quartz fabric-reinforced polymer composites, instead of conventional glass composites. Less attention has been focussed on other important requirements, e.g., out-of-plane (Z-axis) expansion, glass transition temperature (Tg), dielectric constant, and resin microcracking, which also play important roles in the overall performance of the substrate materials. For example, high Z-expansion puts additional strain on the plated through holes (PTH), thereby affecting PTR reliability. A low Tgsignificantly increases the amount of thermal stress imposed during thermal cycling on solder joints and PTH, and leads to failures. This paper contains a brief review of the requirements of a SMT-PCB substrate material, including such critical parameters as: in-plane CTE, out-of-plane CTE, Tg, dielectric constant, fiber-to-resin ratio, and resin microcracking, and their effects on solder joint reliability, PTH reliability, dimensional stability, and electrical performance.