Statistical Static Timing Analysis Research Articles

Statistical static timing analysis using symbolic event propagation

Accurate estimation of critical path delays in circuits is a challenging task, particularly when variations due to manufacturing are considered. For small circuits (such as standard cells), simulation-based characterisation is preferred for better accuracy. For large circuits, statistical timing analysis techniques are used, but these methods typically yield a pessimistic overestimate. In view of the growing size of custom cell designs, an intermediate approach is required -one that can scale to circuits of moderate size and can produce more accurate estimates than traditional static timing analysis methods. A new method is presented that combines symbolic event propagation with statistical timing analysis and thereby achieves a significant level of accuracy with acceptable computational overhead. The benefits of the new style of analysis over the ISCAS'89 benchmark circuits are demonstrated.

Correlation-Preserved Statistical Timing With a Quadratic Form of Gaussian Variables

A recent study shows that the existing first-order canonical timing is not sufficient to represent the dependency of the gate/wire delay on the processing and operational variations when these variations become more and more significant. Due to nonlinear mapping from variation sources to the gate/wire delay, the distribution of the delay will no longer be Gaussian even if variation sources are normally distributed. A novel timing model is proposed to capture the nonlinearity of the dependency of gate/wire delays and arrival times on the variation sources. Systematic methodology is also developed to evaluate the correlation and distribution of the quadratic timing model. Based on these, a statistical static timing analysis algorithm that retains the complete correlation information during timing analysis and has linear computation complexity with respect to both the circuit size and the number of variation sources is proposed. Tested on the ISCAS circuits, the proposed algorithm shows significant accuracy improvement over the existing first-order algorithm with a small amount of computational cost

Statistical Timing Yield Optimization by Gate Sizing

In this paper, we propose a statistical gate sizing approach to maximize the timing yield of a given circuit, under area constraints. Our approach involves statistical gate delay modeling, statistical static timing analysis, and gate sizing. Experiments performed in an industrial framework on combinational International Symposium on Circuits and Systems (ISCAS'85) and Microelectronics Center of North Carolina (MCNC) benchmarks show absolute timing yield gains of 30% on the average, over deterministic timing optimization for at most 10% area penalty. It is further shown that circuits optimized using our metric have larger timing yields than the same optimized using a worst case metric, for iso-area solutions. Finally, we present an insight into statistical properties of gate delays for a commercial 0.13-mum technology library which intuitively provides one reason why statistical timing driven optimization does better than deterministic timing driven optimization

Statistical timing analysis using levelized covariance propagation considering systematic and random variations of process parameters

Variability in process parameters is making accurate timing analysis of nano-scale integrated circuits an extremely challenging task. In this article, we propose a new algorithm for statistical static timing analysis (SSTA) using levelized covariance propagation (LCP). The algorithm simultaneously considers the effect of die-to-die variations in process parameters as well as within-die variation, including systematic and random variations. In order to efficiently handle complicated process variation models while contending with the arbitrary correlation among timing signals, we employ a compact form of the levelized statistical data structure. Furthermore, we propose two enhancements to the LCP algorithms to the make it practical for the analysis of large sized circuits. Results on several ISCAS'85 benchmark circuits in predictive 70nm technology show an average of 0.19% and 0.57% errors in the mean and standard deviation, respectively, of timing analysis using the proposed technique, as compared to the Monte Carlo-based approach.

Statistical static timing analysis with conditional linear MAX/MIN approximation and extended canonical timing model

An efficient and accurate statistical static timing analysis (SSTA) algorithm is reported in this paper, which features 1) a conditional linear approximation method of the MAX/MIN timing operator, 2) an extended canonical representation of correlated timing variables, and 3) a variation pruning method that facilitates intelligent tradeoff between simulation time and accuracy of simulation result. A special design focus of the proposed algorithm is on the propagation of the statistical correlation among timing variables through nonlinear circuit elements. The proposed algorithm distinguishes itself from existing block-based SSTA algorithms in that it not only deals with correlations due to dependence on global variation factors but also correlations due to signal propagation path reconvergence. Tested with the International Symposium on Circuits and Systems (ISCAS) benchmark suites, the proposed algorithm has demonstrated very satisfactory performance in terms of both accuracy and running time. Compared with Monte-Carlo-based statistical timing simulation, the output probability distribution got from the proposed algorithm is within 1.5% estimation error while a 350 times speed-up is achieved over a circuit with 5355 gates

What is statistical design?

In the nanoscale regime, the effects of variations can dramatically affect circuit behavior. These variations may arise from fluctuations in the manufacturing process (e.g., drifts in channel length, oxide thickness, threshold voltage, or doping concentration), which affect the circuit yield, as well as variations in the environmental operating conditions (e.g., supply voltage, temperatures, or particle strikes that lead to soft errors) after the circuit is manufactured, which affect the correctness of the behavior of the design. Some of these variations are entirely deterministic (metal fill density, etc.), while others are random, as their cause is either unknown, or unattributable, or too difficult to model.Circuit performance is known to vary significantly under process and environmental variations: significant changes in timing can result, and the leakage power, which depends exponentially on process parameters, can be greatly affected. Unlike traditional deterministic analysis, where performance values at worst-case process/voltage/temperature corners are computed, statistical analysis determines the probability distributions for the timing or the power.Practical statistical static timing analysis (SSTA) methods proceed in a block-based manner in the fashion of deterministic STA algorithms, and use determine the probability distributions of the arrival time at the gate outputs, while statistical leakage power analysis techniques use probabilistic methods to determine the distribution of the leakage. The performance yield can be computed by using these distributions to determine the fraction of manufactured circuits that satisfy timing and power constraints. Statistical optimization changes the design parameters of the circuit to improve the performance yield.