Statistical Static Timing Analysis Research Articles

A 28 nm 0.6 V Low Power DSP for Mobile Applications

Processors for next generation mobile devices will need to operate across a wide supply voltage range in order to support both high performance and high power efficiency modes of operation. However, the effects of local transistor threshold (VT) variation, already a significant issue in today's advanced process technologies, and further exacerbated at low voltages, complicate the task of designing reliable, manufacturable systems for ultra-low voltage operation. In this paper, we describe a 4-issue VLIW DSP system-on-chip (SoC), which operates at voltages from 1.0 V down to 0.6 V. The SoC was implemented in 28 nm CMOS, using a cell library and SRAMs optimized for both high-speed and low-voltage operating points. A new statistical static timing analysis (SSTA) methodology was also used on this design, in order to more accurately model the effects of local VT variation and achieve a reliable design with minimal pessimism.

A Body Bias Clustering Method for Low Test-Cost Post-Silicon Tuning

Post-silicon tuning is attracting a lot of attention for coping with increasing process variation. However, its tuning cost via testing is still a crucial problem. In this paper, we propose tuning-friendly body bias clustering with multiple bias voltages. The proposed method provides a small set of compensation levels so that the speed and leakage current vary monotonically according to the level. Thanks to this monotonic leveling and limitation of the number of levels, the test-cost of post-silicon tuning is significantly reduced. During the body bias clustering, the proposed method explicitly estimates and minimizes the average leakage after the post-silicon tuning. Experimental results demonstrate that the proposed method reduces the average leakage by 25.3 to 51.9% compared to non clustering case. In a test case of four clusters, the number of necessary tests is reduced by 83% compared to the conventional exhaustive test approach. We reveal that two bias voltages are sufficient when only a small number of compensation levels are allowed for test-cost reduction. We also give an implication on how to synthesize a circuit to which post-silicon tuning will be applied. key words: post-silicon tuning, body bias clustering, process variation, body biasing, statistical static timing analysis

SAMPLING CORRELATION SOURCES FOR TIMING YIELD ANALYSIS OF SEQUENTIAL CIRCUITS WITH CLOCK NETWORKS

Analyzing timing yield under process variations is difficult because of the presence of correlations. Reconvergent fan-out nodes (RFONs) within combinational subcircuits are a major source of topological correlation. We identify two more sources of topological correlation in clocked sequential circuit: sequential RFONs, which are nodes within a clock network where the clock paths to more than one flip-flop branch out; and sequential branch-points, which are nodes within a combinational block where combinational paths to more than one capturing flip-flop branch out. Dealing with all sources of correlation is unacceptably complicated, and we therefore show how to sample a handful of correlation sources without sacrificing significant accuracy in the yield. A further reduction in computation time can be obtained by sampling only those nodes that are likely to affect the yield. These techniques are applied to yield analysis using statistical static timing analysis based on discrete random variables and also to yield analysis based on Monte Carlo simulation; the accuracy and efficiency of both methods are assessed using example circuits. The sequential RFONs suggest that timing yield may be improved by optimizing the clock network, and we address this possibility.

Inclusion of Chemical-Mechanical Polishing Variation in Statistical Static Timing Analysis

Technology trends show the importance of modeling process variation in static timing analysis. With the advent of statistical static timing analysis (SSTA), multiple independent sources of variation can be modeled. This paper proposes a methodology for modeling metal interconnect process variation in SSTA. The developed methodology is applied in this study to investigate metal variation in SSTA resulting from chemical-mechanical polishing (CMP). Using our statistical methodology, we show that CMP variation has a smaller impact on chip performance as compared to other factors impacting metal process variation.

Voltage and Temperature-Aware SSTA Using Neural Network Delay Model

With the emergence of voltage scaling as one of the most powerful power reduction techniques, it has been important to support voltage scalable statistical static timing analysis (SSTA) in deep submicrometer process nodes. In this paper, we propose a single delay model of logic gate using neural network which comprehensively captures process, voltage, and temperature variation along with input slew and output load. The number of simulation programs with integrated circuit emphasis (SPICE) required to create this model over a large voltage and temperature range is found to be modest and 4× less than that required for a conventional table-based approach with comparable accuracy. We show how the model can be used to derive sensitivities required for linear SSTA for an arbitrary voltage and temperature. Our experimentation on ISCAS 85 benchmarks across a voltage range of 0.9-1.1 V shows that the average error in mean delay is less than 1.08% and average error in standard deviation is less than 2.85%. The errors in predicting the 99% and 1% probability point are 1.31% and 1%, respectively, with respect to SPICE. The two potential applications of voltage-aware SSTA have been presented, i.e., one for improving the accuracy of timing analysis by considering instance-specific voltage drops in power grids and the other for determining optimum supply voltage for target yield for dynamic voltage scaling applications.

STATISTICAL TIMING ANALYSIS OF THE CLOCK PERIOD IMPROVEMENT THROUGH CLOCK SKEW SCHEDULING

Statistical static timing analysis (SSTA) methods, which model process variations statistically as probability distribution function rather than deterministically, have been thoroughly performed on traditional zero clock skew circuits. In the traditional zero clock skew circuits, the synchronizing clock signal is designed to arrive in phase with respect to each register. However, designers will often schedule the clock skew to different registers in order to decrease the minimum clock period of the entire circuit. Clock skew scheduling imparts very different timing constraints that are based, in part, on the topology of the circuit. In this paper, SSTA is applied to nonzero clock skew circuits in order to determine the accuracy improvement relative to their zero skew counterparts, and also to assess how the results of skew scheduling might be impacted with more accurate statistical modeling. For 99.7% timing yield (3σ variation), SSTA is observed to improve the accuracy, and therefore increase the timing margin, of nonzero clock skew circuits by up to 2.5×, and on average by 1.3×, the amount seen by zero skew circuits.

A General Framework to Perform the MAX/MIN Operations in Parameterized Statistical Timing Analysis Using Information Theoretic Concepts

As integrated circuit technologies are scaled down to the nanometer regime, process variations have increasing impact on circuit timing. To address this issue, parameterized statistical static timing analysis (SSTA) has been recently developed. In parameterized SSTA, process variations are represented as random variables (RVs) and timing quantities (delays and others) are expressed as functions of these variables. Most of the existing algorithms to compute the <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">MAX</i> / <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">MIN</i> operations in parameterized SSTA model spatial and path-based statistical dependencies of variation sources using the second-order statistical methods. Unfortunately, such methods have limited capabilities to determine statistical relations between RVs. This results in decreasing the accuracy of the <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">MAX</i> / <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">MIN</i> algorithms, especially when process parameters follow non-Gaussian probability density functions (PDFs) and/or affect timing quantities nonlinearly. In contrast, information theory (IT) provides powerful techniques that allow a natural PDF-based analysis of probabilistic relations between RVs. So, in this paper, we propose a new framework to perform the <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">MAX</i> / <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">MIN</i> operations based on IT concepts. The key ideas behind our framework are: 1) exploiting information entropy to measure unconditional equivalence between an actual <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">MAX</i> / <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">MIN</i> output and its approximate parameterized representation, and 2) using mutual information to measure equivalence of actual and parameterized <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">MAX</i> / <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">MIN</i> outputs from the viewpoint of their statistical relations to process variations. We construct a general IT-based <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">MAX</i> / <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">MIN</i> algorithm that allows a number of particular realizations accounting for statistical properties of parameterized RVs. The experimental results validate the correctness and demonstrate a high accuracy of the new IT-based approach to compute the <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">MAX</i> / <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">MIN</i> .

On modeling the digital gate delay under process variation

To achieve a characterization method for the gate delay library used in block based statistical static timing analysis with neither unacceptably poor accuracy nor forbiddingly high cost, we found that general-purpose gate delay models are useful as intermediaries between the circuit simulation data and the gate delay models in required forms. In this work, two gate delay models for process variation considering different driving and loading conditions are proposed. From the testing results, these two models, especially the one that combines effective dimension reduction (EDR) from statistics society with comprehensive gate delay models, offer good accuracy with low characterization cost, and they are thus competent for use in statistical timing analysis (SSTA). In addition, these two models have their own value in other SSTA techniques.

Fast Statistical Static Timing Analysis Using Smart Monte Carlo Techniques

In this paper, we propose a stratification+hybrid quasi Monte Carlo (SH-QMC) approach to improve the efficiency of Monte Carlo-based statistical static timing analysis (SSTA) using sample size reduction. Sample size reduction techniques proposed in the literature exhibit a tradeoff between accuracy of the Monte Carlo estimate with fewer samples and their ability to handle large number of variables in multidimensional space. This paper proposes to target several such techniques to different sets of process variation variables by using information about the importance of these variables to the circuit delay, and the capability of the techniques to handle multiple dimensions. Simulations on benchmark circuits up to 90 K gates show that the proposed method requires up to 224 samples for varying levels of process variation to achieve accurate timing estimates. Results also show that when SH-QMC is performed with multiple parallel threads on a quad-core processor, the approach is faster than traditional SSTA with comparable accuracy. When the proposed SH-QMC technique is supplemented with a graph pruning method the runtime is further reduced by 46-48% on average. The technique is also extended to include an incremental approach to recompute a percentile delay metric after engineering change order.

An accurate sparse-matrix based framework for statistical static timing analysis

Statistical static timing analysis has received wide attention recently and emerged as a viable technique for manufacturability analysis. To be useful, however, it is important that the error introduced in SSTA be significantly smaller than the manufacturing variations being modeled. Achieving such accuracy requires careful attention to the delay models and to the algorithms applied. In this paper, we propose a new sparse-matrix based framework for accurate path-based SSTA, motivated by the observation that the number of timing paths in practice is sub-quadratic based on a study of industrial circuits and the ISCAS89 benchmarks. Our sparse-matrix based formulation has the following advantages: (a) it places no restrictions on process parameter distributions; (b) it can use an accurate polynomial-based delay model which takes into account slope propagation naturally; (c) it takes advantage of the matrix sparsity and high performance linear algebra for efficient implementation. Our experimental results are very promising.

Scheduling and Resource Binding Algorithm Considering Timing Variation

The timing closure problem (e.g., meeting timing/clock period constraint) is one of the most important problems in the design automation. However, the rapid increase of the impact of the process variation on circuit timing makes the problem much more complicated and unpredictable to tackle in synthesis. This paper addresses a new problem of high-level synthesis (HLS) that effectively takes into account the timing variation. Conventional HLS may simply avoid the timing variation problem by considering the worst case or constant delay model of hardware resources, which are certainly not viable solutions. To overcome the impact of timing variation in HLS, this paper addresses the following two problems: 1) how can the statistical static timing analysis (SSTA) used in logic synthesis be modified and effectively applied to the delay and yield computation in HLS? and 2) how can scheduling and resource binding tasks effectively solve the HLS problem with the objective of minimizing latency under yield constraint? Through an extensive experimentation, we confirm that the proposed variation-aware HLS algorithm is able to reduce the latency by 19.7% under 90% performance yield constraint, compared with the result by conventional timing variation-unaware HLS .

Binning Optimization for Transparently-Latched Circuits

With increasing process variation, binning has become an important technique to improve the values of fabricated chips, especially in high performance microprocessors where transparent latches are widely used. In this paper, we formulate and solve the binning optimization problem that decides the bin boundaries and their testing order to maximize the profit (considering the test cost) for a transparently-latched circuit. The problem is decomposed into four sub-problems. First, to compute the clock period distribution of the transparently-latched circuit, a sample-based statistical static timing analysis (SSTA) approach is developed which is based on the generalized stochastic collocation method with the sparse grid technique. The minimal clock period on each sample point is found by solving a minimal cycle ratio problem in the constraint graph. Second, a greedy method is proposed to maximize profit considering both the sales revenue and the test cost by iteratively assigning each boundary to its optimal position. Third, an optimal algorithm of O(n log n) runtime is used to generate the optimal testing order to minimize the test cost, based on alphabetic tree. Last, a simple approach is presented to decide the optimal number of bins, which helps to complete the whole binning scheme with maximal profit. Experiments on all the ISCAS'89 sequential benchmarks with 65 nm technology show 10.68% profit improvement in average. Some comparisons with other methods suggest the advantage of our method. The results also demonstrate that the proposed SSTA method achieves an error of 0.70% and speedup of 110X in average compared with the Monte Carlo simulation.

Bound-Based Statistically-Critical Path Extraction Under Process Variations

This paper introduces a bound-based approach to extract a pre-specified number of statistically-critical paths under process variations. These are the paths with the highest “violation probability,” which indicates the probability that a path would violate a given timing constraint. Our approach requires pre-computation of the violation probability of all the nodes and edges in the circuit timing graph, which can be done using two rounds of block-based statistical static timing analysis. Given these node/edge violation probabilities, we derive tight upper and lower bounds for any arbitrary segment of consecutive nodes and edges, which is the major contribution of this paper. We further utilize these bounds to extract the statistically-critical paths and show constant-time for incremental update of the bounds when extending a segment to a longer one. If our goal is to extract the single most statistically-critical path, we show a bound-based reduction that can prune a large portion of circuit without losing optimality. In our simulations, we verify the correctness and accuracy of our bounds for individual paths, and compare with exact path extraction using Monte-Carlo-based simulation, and an alternative which incorporates path-based statistical static timing analysis.

Variation-Aware Placement With Multi-Cycle Statistical Timing Analysis for FPGAs

Deep submicron processes have allowed field-programmable gate arrays (FPGAs) to grow in complexity and speed. However, such technology scaling has caused FPGAs to become more susceptible to the effects of process variation. In order to obtain sufficient yield values, it is now necessary to consider process variation during physical design. It is common for FPGAs to contain designs with multi-cycle paths to help increase the performance, but current statistical static timing analysis (SSTA) techniques cannot support this type of timing constraint. In this paper, we propose an extension to block-based SSTA to consider multi-cycle paths. We then use this new SSTA to optimize FPGA placement with our tool VMC-Place for designs with multi-cycle paths. Experimental results show our multi-cycle SSTA is accurate to 0.59% for the mean and 0.0024% for the standard deviation. Our results also show that VMC-Place is able to reduce the 95% performance yield clock period by 15.36% as compared to VPR.

Statistical analysis of time delays multiprocessor systems

In this paper a method of statistical static timing analysis (SSTA) for multicore processors is proposed. An effective method of timing analysis based on simultaneous application of usual static as well as statistical static timing analysis. At the first stage usual static timing analysis (STA) is applied and at the second stage - SSTA. The proposed method of analysis allows reaching of acceptable analysis results from the practical viewpoint of accuracy at considerably small expenses of machine runtime

Process variation-aware performance analysis of asynchronous circuits

Current technology trends have led to the growing impact of process variations on performance of asynchronous circuits. As it is imperative to model process parameter variations for sub-100nm technologies to produce a more real performance metric, it is equally important to consider the correlation of these variations to increase the accuracy of the performance computation. In this paper, we present an efficient method for performance evaluation of asynchronous circuits considering inter- and intra-die process variation. The proposed method includes both statistical static timing analysis (SSTA) and statistical Timed Petri-Net based simulation. Template-based asynchronous circuit has been modeled using Variant-Timed Petri-Net. Based on this model, the proposed SSTA calculates the probability density function of the delay of global critical cycle. The efficiency for the proposed SSTA is obtained from a technique that is derived from the principal component analysis (PCA) method. This technique simplifies the computation of mean, variance and covariance values of a set of correlated random variables. In order to consider spatial correlation in the Petri-Net based simulation, we also include a correlation coefficient to the proposed Variant-Timed Petri-Net which is obtained from partitioning the circuit. We also present a simulation tool of Variant-Timed Petri-Net and the results of the experiments are compared with Monte Carlo simulation-based method.

Resource Sharing Problem of Timing Variation-Aware Task Scheduling and Binding in MPSoC

This work addresses the new problem of timing variation-aware (TV) task scheduling and binding (TSB) for multiprocessor system-on-chip (MPSoC) architecture in the system-level design, where tasks have the full flexibilities of resource (i.e. processor) sharing to meet the design constraints. With the timing variation of processors’ clock speed, it has been observed that the consideration of the effect of resource sharing on the resulting performance yield computation is critically important for accurate design space exploration and evaluation in the system-level design. Nevertheless, unfortunately the previous statistical static timing analysis (SSTA) in the system level has never considered the resource sharing in the performance yield computation, or has overly simplified it by employing the gate-level SSTAs. In this work, we overcome this limitation of the previous work. Specifically, under the data of clock speed variation of each processor, we propose an effective technique of SSTA, called TSB-SSTA, on TSB in the presence of resource sharing and develop a TV framework, called TSB-TV, of TSB that tightly integrates TSB-SSTA. Through experimentation with the benchmark designs, we have tested the effectiveness of our approach. In summary, compared with the results by the conventional TV TSB, TSB-TV enhances the performance yield of designs by 30% on average.

Efficient and realistic statistical worst case delay computation using VHDL

A method for worst case path-delay estimation in complex digital circuits is presented. It has been named Statistical Static Timing Analysis Using a Standard Logic Simulator (SSTA for SLog). It enables acceleration of algorithmically simple but computationally expensive and time-consuming Monte-Carlo simulations. The technique deals with fabrication-dependent delay variations of a particular technology. It applies a realistic rise/fall delay model with fanout dependent delays based on technology and implementation data.

Adjustment-Based Modeling for Timing Analysis Under Variability

This paper presents an adjustment-based modeling framework for timing analysis under variability. Instead of building a complex model (such as polynomial one) directly between the circuit timing and parameter variability, we propose to build a model that adjusts an approximate variation-aware timing into an accurate one. The idea is that it is easier to build a model that adjusts an approximate estimate into an accurate one. In addition, it is more efficient to obtain an approximate circuit timing model. The combination of these two observations makes the use of an adjustment-based model a better choice for statistical static timing analysis with high dimension of parameter variability (e.g., at sign-off stage). It can also be used at the postsilicon stage to predict the circuit timing from a smaller subcircuit. To build the adjustment model, we use a simulation-driven approach based on Gaussian Process. Combined with the intelligent sampling, we show that an adjustment-based model can more effectively capture the nonlinearity of the circuit timing with respect to parameter variability compared to polynomial models. Simulation results show that with 42 independent device and interconnect parameter variations, our proposed adjustment-based model obtained using 200 circuit timing samples can achieve much higher accuracy than quadratic model obtained using 2000 samples.

An On-the-Fly Parameter Dimension Reduction Approach to Fast Second-Order Statistical Static Timing Analysis

While first-order statistical static timing analysis (SSTA) techniques enjoy good runtime efficiency desired for tackling large industrial designs, more accurate second-order SSTA techniques have been proposed to improve the analysis accuracy, but at the cost of high computational complexity. Although many sources of variations may impact the circuit performance, considering a large number of inter- and intra-die variations in the traditional SSTA is very challenging. In this paper, we address the analysis complexity brought by high parameter dimensionality in SSTA and propose an accurate yet fast second-order SSTA algorithm based on novel on-the-fly parameter dimension reduction techniques. By developing a reduced rank regression (RRR)-based approach and a method of moments (MOM)-based parameter reduction algorithm within the block-based SSTA flow, we demonstrate that accurate second-order SSTA can be extended to a much higher parameter dimensionality than what is possible before. Our experimental results have shown that the proposed parameter reductions can achieve up to 10times parameter dimension reduction and lead to significantly improved second-order SSTA under a large set of process variations.