Efficient and realistic statistical worst case delay computation using VHDL

Abstract

A method for worst case path-delay estimation in complex digital circuits is presented. It has been named Statistical Static Timing Analysis Using a Standard Logic Simulator (SSTA for SLog). It enables acceleration of algorithmically simple but computationally expensive and time-consuming Monte-Carlo simulations. The technique deals with fabrication-dependent delay variations of a particular technology. It applies a realistic rise/fall delay model with fanout dependent delays based on technology and implementation data.