Abstract
Accurate estimation of critical path delays in circuits is a challenging task, particularly when variations due to manufacturing are considered. For small circuits (such as standard cells), simulation-based characterisation is preferred for better accuracy. For large circuits, statistical timing analysis techniques are used, but these methods typically yield a pessimistic overestimate. In view of the growing size of custom cell designs, an intermediate approach is required -one that can scale to circuits of moderate size and can produce more accurate estimates than traditional static timing analysis methods. A new method is presented that combines symbolic event propagation with statistical timing analysis and thereby achieves a significant level of accuracy with acceptable computational overhead. The benefits of the new style of analysis over the ISCAS'89 benchmark circuits are demonstrated.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.