Static Random Access Memory Bit Research Articles

Investigating the Impact of Technology Scaling on Stability Performance of Sub-threshold Static Random Access Memory Bitcell Topologies

Static random-access memory (SRAM) is increasingly being used in VLSI circuits as a result of the development of portable devices. As the demand for low-power devices increases, sub-threshold operation of SRAMs has become a popular method to reduce power consumption but at the cost of reduced stability. The work aims to propose design parameters for SRAM bit cell topologies- 6T and 10T with proper device sizing and to investigate the impact of technology scaling on its stability performance in the sub threshold region. Moreover, analysis demonstrates the impact of variations of device sizing in terms of Cell ratio and Pull up ratio on stability margins of designed SRAM topologies. Simulations are carried out in the HSPICE environment using 16 nm and 22 nm CMOS process nodes. We find that the stability margins of 10T SRAM cell outperform the 6T SRAM cell; however stability margin decreases with decreasing technology nodes. The Read Static Noise Margin (RSNM) and Write Static Noise Margin (WSNM) of 10T SRAM cell is improved by 48.38% and 308.64% respectively in 22nm and 53.04% and 243.93% respectively in 16nm process technology as compare to 6T SRAM cell.

Single ended 12T cntfet sram cell with high stability for low power smart device applications

Static random-access memory (SRAM) is the most prevalent type of memory used in current system-on-chips (SOC). SRAMs built using Complementary metal oxide semiconductor (CMOS) transistors, suffer from low stability and significant power dissipation at nano scale regime [1]. Studies show that the Carbon nanotube field effect transistor (CNTFET) are prominent to use at nano scale region. This article proposes a 12T CNTFET SRAM cell and its performance metrics like power, stability and delay are compared with various other recent SRAM cells by simulating them using CNTFETs. Two Schmitt trigger (ST) based cross coupled inverter arrangement make up the storage cell in the suggested 12T CNTFET SRAM bit cell. ST-based inverter has stacked N-type transistors, which reduces the circuit's leakage and the voltage transfer characteristics (VTC) of ST inverter is also sharper than the other conventional inverters, thereby enhancing the stability performance of the proposed bit cell. The cell also uses feedback cutting transistor and a separate read and write path to further improve the stability performances during read and write modes. The suggested 12T CNTFET SRAM cell shows higher write SNM, hold SNM and read SNM when compared to other state of the art SRAM cells. The read and write delay of the proposed 12T CNTFET SRAM cell is also seen to improve in contrast to the other SRAM designs. The proposed 12T CNTFET SRAM cell when simulated using 32 nm CNTFET at 0.9 V, shows write power, hold power, read power, write delay, read delay, write static noise margin (WSNM), HSNM and read static noise margin (RSNM), as 0.19 nW, 1.61 nW, 3.13 µW, 119 pS, 7.33 pS, 444 mV, 420 mV, 420 mV respectively. The suggested cell is also tested for parametric variations and its performance is also recorded. The proposed cell surpasses all other cells considered as far as power and stability are concerned making it suitable for usage in smart devices like smart bands, smart watches etc. A 32 nm Stanford University model is used to simulate the proposed 12T CNTFET SRAM cell using the HSPICE tool.

Stability Parameters of Register File Bit Cell with Low Power Consumption Priority

This research is dedicated to a transistor sizing method of an 8-transistor register file static random access memory bit cell aiming to create two-port register files and two-port static random access memory with reduced supply voltage to reduce power consumption. This method can also be applied to 6-transistor single-port static random access memory bit cells. The method is based on the analysis of butterfly curves and the search for such values of the sizes of transistors and margin of their threshold voltages, in which, for a given critical minimal supply voltage, the condition for the existence of one intersection and one touch of its curves is achieved for the butterfly curves. The obtained samples of the register files bit cell in silicon and its critical voltage were compared to the results of circuit simulation in the write and read mode depending on the supply voltage. Experimental register files chip samples were successfully tested in silicon at a voltage of 0.75 V.

PUF-CIM: SRAM-Based Compute-In-Memory With Zero Bit-Error-Rate Physical Unclonable Function for Lightweight Secure Edge Computing

With the rapid development of the Internet of Things (IoT), compute-in-memory (CIM) is a promising candidate for edge computing, which eliminates the need for frequent data transfer between the memory and processing units. On one hand, CIM provides an efficient approach to achieve deep neural network (DNN) inference; on the other hand, its security issues such as model leakage are ignored in most of state-of-the-art studies. In the resource-limited conditions, it is essential to develop a lightweight secure scheme for CIM without significantly sacrificing its performance. In this work, a physical unclonable function (PUF)-CIM macro based on static random access memory (SRAM) is proposed for lightweight model protection. An SRAM-based PUF extracts unique and stable keys from the mismatch of multirow discharge rate and further achieves zero bit error rate (BER) under temperature and voltage fluctuations by the on-chip masking technique. Besides, we propose a 10T SRAM bit cell to perform xor operation and multiply-and-accumulate (MAC) operation in the same cell, which avoids weight movement during encryption and decryption. The whole process including key generation, xor encryption, and ciphertext MAC operation has been realized. The test chip is designed and fabricated in a 55-nm CMOS process. Experimental results show that the proposed PUF with on-chip masking can provide zero unstable bits and BER under temperature and voltage variations. The proposed PUF-CIM achieves 96.20% inference accuracy in MNIST. Besides, it presents 93.35–121.38-TOPS/W energy efficiency and 1324.24-GOPS throughput. Compared with the normal CIM, the proposed PUF-CIM can enhance AI model security, only with accuracy loss of 1% and energy efficiency degradation of 16.1%.

High-Stability and High-Speed 11T CNTFET SRAM Cell for MIMO Applications

Many researchers are actively working on developing a fast-performing static random-access memory (SRAM) cell with low-power consumption and high stability. This study also introduces one such new and all-round excellent SRAM cell. In this paper, an SRAM cell with eleven transistors (11T) developed using carbon nanotube field effect transistor (CNTFET) is introduced. This new 11T CNTFET SRAM cell is another variant of the Schmitt-trigger (ST)-based SRAM cell. This new SRAM cell structure is achieved by incorporating a single-ended write mode, a feed-back cutting technique and a single-ended read approach into a Schmitt-trigger (ST)-based SRAM cell. The WSNM of the proposed 11T CNTFET SRAM cell is increased by using single-ended writing scheme and feed-back cutting method in the cell. The single ended read approach of 11T CNTFET SRAM cell increases the RSNM as the storage nodes are not disturbed. The write power, hold power, read power, WSNM, HSNM, RSNM, write delay and read delay of this 11T CNTFET SRAM cell are 2.1538e-10 W, 1.7077e-09 W, 1.4524e-08 W, 423.61 mV, 402.20 mV, 425.56 mV, 1.2932e-10s and 5.5225e-12s, respectively. The parameters of the proposed cell are compared with 6T SRAM [M. Elangovan and K. Gunavathi, Stability analysis of 6T CNTFET SRAM cell for single and multiple CNTs, 2018 4th Int. Conf. Devices, Circuits Syst., Coimbatore, India, 16–17 March 2018, vol. 2, pp. 63–67], 8T SRAM [M. Elangovan, A novel Darlington based 8T CNTFET SRAM cell for low, J. Circuits Syst. Comput. 30 (2021) 2150213], 12T SRAM [S. Pal, S. Bose, W. H. Ki and A. Islam, Half-select-free low-power dynamic loop-cutting write assist SRAM cell for space applications, IEEE Trans. Electron Dev. 67 (2020) 80–89, doi:10.1109/TED.2019.2952397], 12T SRAM [N. Yadav, A. P. Shah and S. K. Vishvakarma, Stable, reliable, and bit-interleaving 12T SRAM for space applications: A device circuit co-design, IEEE Trans. Semicond. Manuf. 30 (2017) 276–284, doi:10.1109/TSM.2017.2718029], 12T SRA-M [P. Sharma, S. Gupta, K. Gupta and N. Pandey, A low power subthreshold Schmitt Trigger-based 12T SRAM bit cell with process-variation-tolerant write-ability, Microelectron. J. 97 (2020) 104703, doi:10.1016/j.mejo.2020.104703] and 12T SRAM [P. Sharma, S. Gupta, K. Gupta and N. Pandey, A low power subthreshold Schmitt Trigger based 12T SRAM bit cell with process-variation-tolerant write-ability, Microelectron. J. 97 (2020) 104703, doi:10.1016/j.mejo.2020.104703] cells to understand the performance of the proposed SRAM cell. From the comparative study, it is observed that the proposed cell is more stable than the other cells considered for the comparison and consumes less power in all write, read and hold modes. Also, the read time of the introduced cell is much less than the others. This study also recorded the information on how the performance of an SRAM cell varies as the CNTFET parameters change. The simulation is done with the HSPICE simulation tool using the Stanford University 32[Formula: see text]nm CNTFET model.

Stability and Power Analysis of Schmitt Trigger Based Low Power SRAM Bit-Cell Using CMOS and CNTFET Technology at 22nm Technology Node

SRAM (Static Random Access Memory) is an essential component of memory devices such as laptops, phones, etc., which act as a semiconductor memory. The “Carbon Nanotube Field Effect Transistor (CNTFET)” is silicon associated high-stability, low-power device with excellent performance. CNTFET has been verified to be very advantageous for Very large-scale integration circuit designs in the nanoscale range because of its remarkable properties of metal oxide semiconductor field effect transistor (MOSFET). The material was brought to light because of its genuinely incredible electrochemical performance. Carbon nanotubes have unique properties such as high charge carrier mobility, high voltage, small footprint, exceptionally short and high control over pulse duration, and large current densities. In traditional MOSFET, bulk silicon is used, which has high leakage current and high field-effect; thus, CNTFET has been used as an alternative in recent years. When compared to the 10T CNTFET SRAM Bit cell is designed using HSPICE Tool in 22nm technology. Long-term stability and significant process variable changes are significant challenges with nanoscale SRAM cells.

Reliability improved dual driven feedback 10T SRAM bit cell

This paper presents a dual driven feedback 10T (DDFB10T) static random-access memory (SRAM) bit cell with good read and write stability and that is free from half select issue. This DDFB10T cell working at VDD = 0.9 V achieves 1.5× higher static voltage noise margin (SVNM), and 0.48× lesser write trip voltage (WTV) than 6T SRAM cell. Monte Carlo simulation employing local and global variation using Cadence Virtuoso tool with 45 nm technology proves that the proposed bit cell is highly immune against process, voltage, and temperature (PVT) variations. The proposed DDFB10T bit cell exhibits lesser SVNM variability when it is normalized to that of 6T SRAM bit cell. The proposed DDFB10T cell is designed with the capability to provide a bit interleaved architecture for reducing half select issues.

Performance Analysis of 9T SRAM using 180nm, 90nm, 65nm, 32nm, 14nm CMOS Technologies

The growing markets for low-power electronic devices energized by battery have created the need for smaller power-efficient chips to prevent frequent charging of the source. Nowadays the market capitalization of low-power appliances is expected to grow from USD 4.9 billion by 2022 to USD 7.9 billion by 2027 as per global forecast to 2027 published by markets. The main factor leading to growth of low power electronics market includes demand of energy saving components, miniaturization, and entry of IoT (internet of things) devices. In addition, increased investment by automotive OEM (Original Equipment Manufacturer) and governments to promote the adoption of electric vehicles is expected to create more market opportunities. In this digital era, memory components play a major role in power consumption and this incites the research interest these days. CMOS (Complementary Metal Oxide Semiconductor) technology is growing rapidly towards greater integration into a single chip, resulting to a decrease in chip sizes using less space. Speed and stability demand is also growing up. Combined chip density increases as downtime technology continues. Stability and reliability are an important issue for the static random access memory (SRAM) memory device. In this paper, the design and analysis of CMOS based 9T SRAM cell in a variety of technologies is presented. The main focus of this review paper is to analyze 9T SRAM to test performance on several CMOS technologies (180nm, 90nm, 65nm, 45nm, 32nm, 14nm) with the help of a predictable technology (PTM) file. The butterfly curve method is used to examine the consistency of the SRAM bit cell in terms of static noise margin (SNM). It is clearly shown in this paper that as it progresses from 180nm to 14nm the delay decreases with stability.

A comprehensive analysis of different 7T SRAM topologies to design a 1R1 W bit interleaving enabled and half select free cell for 32 nm technology node

In this paper, a single-ended, dual port, 1R1 W seven transistor-based static random access memory bit cell is presented. The cell is designed based on a detailed review of various pre-existing 7T cells. All the cells in the paper are evaluated at 32 nm technology and supply voltage of 0.8 V. The static analysis reveals that the hold/read noise margins for the proposed cell are 324 mV each, whereas the write margin is 488 mV. Successful read and write operation for the cell requires a pulse-width of 5 ps and 0.14 ns, respectively. The temperature variation and process corner analysis are used to justify the reliability for the proposed cell. The former analysis yields 0.15 and 0.24 mV/°C variation in the HSNM/RSNM, and WM for the cell. The current ratio for the cell is comparatively higher than other cells. The leakage power consumption for the cell is 256 pW, while its read and write power consumption are 6 µW and 1.9 µW, respectively. Also, the cell is half select disturbance-free and therefore supports bit-interleaving. This ensures the increased reliability for the cell. All the aforementioned merits for the cells are achieved with a minimal layout area of 0.553 µm2.

Secure XOR-CIM Engine: Compute-In-Memory SRAM Architecture With Embedded XOR Encryption

Compute-in-memory (CIM), where information can be processed and stored at the same locations, is emerging as a promising paradigm to address the memory wall bottleneck in traditional Von Neumann architectures. Static random-access memory (SRAM) has been demonstrated as a mature candidate for CIM accelerator for deep neural networks (DNNs) due to its availability in advanced technology nodes. However, as SRAM is volatile and could not hold weight after power down, the necessity for downloading models from the cloud to inference engine causes potential threats such as model leaking. Also, saving raw weights of the DNN model stationary in the memory cells will increase the vulnerabilities. This work aims at developing a secure inference engine with a lightweight yet effective countermeasure to protect the DNN models in SRAM-based CIM architecture. We propose a secure XOR-CIM engine with a modified reverse secure sketch protocol to enable on-chip authentication and key processing for XOR-based stream cipher encrypted models. In the XOR-CIM core, we modify the six-transistor SRAM bit cell with dual wordlines to implement XOR decryption without sacrificing the parallel computation’s efficiency. The evaluations at 28 nm show that the XOR-CIM could enhance security, achieving comparable energy efficiency and no throughput loss, with negligible area overhead compared with the normal-CIM design without encryption.

A low power subthreshold Schmitt Trigger based 12T SRAM bit cell with process-variation-tolerant write-ability

Scaling of supply voltage is a well-received approach to reduce power consumption in Static Random Access Memory (SRAM). However, conventional 6T and 8T SRAMs suffer from degraded stability due to random process variations, thereby limiting voltage scaling. It has been observed that Schmitt Trigger (ST) based SRAMs exhibit much better stability than conventional 6T and 8T SRAMs. However, ST based SRAMs inherently suffer from poor write-ability and therefore, exhibit overall higher VMIN. In this work, we propose a twelve-transistor ST based SRAM bit cell, aimed at enabling process-variation-tolerant write-ability, consequently allowing an overall reduction in VMIN and energy per operation. Simulations on the 32 ​nm process node demonstrate that the proposed SRAM allows up to 188 ​mV reduction in VMIN over previous ST bit cells. This translates to up to 3.65 × and 1.91 × lower energy consumptions than conventional 6T and ST-based SRAMs respectively. With large reductions in energy per operation at VMIN, the proposed SRAM is suitable for ultra-low power applications.

Optimization of n-MOS 6T Nanowire SRAM Bit Cell Based on Nanowires Ratio of SiNWTs

In nowadays technology, the primary memory structure widely used in many digital circuit applications is a six transistor (6T) Static Random Access Memory (SRAM) bit cell. The main reason for minimizing memory bit cell to nanodimensions is to provide the SRAM integrated circuits (ICs) with the possible largest memory size per one chip, and the main unit in 6T SRAM bit cell is the MOSFET. One of the new MOSFET structures that overcome conventional MOSFET structure problems under minimization towards nanodimension is the silicon nanowire transistor (SiNWT). This study is the first to explore and optimize the nanowire ratio of driver to load (KD/KL) for a six n-channel SiNWT-based SRAM bit cell. The MuGFET simulation tool has been used to calculate the output characteristics of each transistor individually, and then these characteristics are implemented in the MATLAB software to produce the final static butterfly and current characteristics of nanowire 6T-SRAM bit cell. The demonstration of the driver to load transistors’ nanowires ratio optimizations of nanoscale n-type SiNWT-based SRAM bit cell has been discussed. In this research, the optimization of KD/KL will strongly depend on inflection voltage and high and low noise margins (NMs) of butterfly characteristics. The improvement of NMs of butterfly characteristics has been done by increasing the drain current (Ids) of the driver transistor. Also, the optimization in principle will depend on whether NMs are equal and high, and the inflection voltage (Vinf) is near to Vdd/2 values as possible. These principles have been used as limiting factors for optimization. The results show that the optimization strongly depends on the nanowire ratio, and the best ratio was KD/KL 4. The increase in KD/KL leads to a continuous increase in NMH, acceptable NML and low percentage increment of static power consumption (ΔP %) at KD/KL 4.

Transistor-level characterization of static random access memory bit failures induced by random telegraph noise

Bit failure events induced by random telegraph noise (RTN) for silicon-on-thin-buried-oxide (SOTB) static random access memory (SRAM) cells were characterized by directly monitoring the storage node voltage of individual cells, using a device-matrix-array (DMA) test element group (TEG). Correlating the cell-level RTN and failure waveforms with the RTN waveforms of individual transistors that constitute the same cell, RTN of a specific transistor that causes the cell failure was identified.

Write Assist Circuit to Cater Reliability and Floating Bit Line Problem of Negative Bit Line Assist Technique for Single or Multiport Static Random Access Memory

We propose adaptive negative bit line write assist (WA) circuit for static random access memory (SRAM). It provides controlled overdrive voltage (or negative bump) across the full range of operating voltage. This allows dynamic voltage and frequency scaling without penalizing the reliability at higher voltage and temperature. Design is implemented in CMOS 32NM low power technology for dual port (DP) SRAM bit cell 0.390u2 (DP390) having a normal operating range from 0.9 to 1.1 V, extended to 0.75-1.1 V by utilizing proposed WA circuit. This design has an area overhead of 4.5%. Write cycle performance improvement and dynamic power reduction achieved is 10% and 8%, respectively, at 0.9 V with respect to the design without WA.

SRAM Array Structures for Energy Efficiency Enhancement

Energy efficiency is a supreme design concern in many ultralow-power applications. In such applications, static random-access memory (SRAM) plays a significant role in energy consumption due to the high density for evermore increased computing power. This brief explores and analyzes SRAM array structures for energy efficiency improvement. In contrast to the traditional practices where SRAM arrays enclose more rows than columns, this work reveals that better SRAM energy efficiencies can be achieved with a wider SRAM array structure with fewer rows than columns particularly at low supply voltage. The analysis shows that the array structure optimization can improve the energy efficiency up to 38% (64 kbit) and 10% (8 kbit) for the same SRAM bit density and the same supply voltage.

Design and Iso-Area $V_{\min}$ Analysis of 9T Subthreshold SRAM With Bit-Interleaving Scheme in 65-nm CMOS

In this brief, a 9T bit cell is proposed to enhance write ability by cutting off the positive feedback loop of a static random-access memory (SRAM) cross-coupled inverter pair. In read mode, an access buffer is designed to isolate the storage node from the read path for better read robustness and leakage reduction. The bit-interleaving scheme is allowed by incorporating the proposed 9T SRAM bit cell with additional write wordlines (WWL/WWLb) for soft-error tolerance. A 1-kb 9T 4-to-1 bit-interleaved SRAM is implemented in 65-nm bulk CMOS technology. The experimental results demonstrate that the test chip minimum energy point occurs at 0.3-V supply voltage. It can achieve an operation frequency of 909 kHz with 3.51-W active power consumption.

Asymmetric Drain Spacer Extension (ADSE) FinFETs for Low-Power and Robust SRAMs

In this paper, we analyze and optimize FinFETs with asymmetric drain spacer extension (ADSE) that introduces a gate underlap only on the drain side. We present a physics-based discussion of current-voltage relationships, short channel effects, and leakage and show the application of ADSE FinFETs in 6T static random access memory (SRAM) bit cell. By exploiting asymmetry in current, we show that it is possible to achieve improvement in both read and write stability for the 6T SRAM bit cell, along with reduction in cell leakage at the cost of negligible increase in access time and area. We also propose a general circuit-aware device optimization methodology for SRAM design. We use this methodology to optimize the underlap in ADSE FinFETs. Compared to conventional FinFETs, we achieve 57% reduction in leakage, 11% improvement in read static-noise margin, and 6% improvement in write margin, with 7% increase in access time and cell area.

Gate etch process model for static random access memory bit cell and FinFET construction

A reactor/feature/lithography modeling suite has been developed to study the gate etch process. The gate etch process study consists of an eight step process designed to etch through a hard mask (HM)/antireflective coating/polysilicon gate stack and a 22+ step modeled process for FinFET (field effect transistor) manufacture. Coupling to a lithography model allows for a study of how a static random access memory (SRAM) bit cell layout transfers into the gate stack during the gate etch process. The lithography model calculates a three-dimensional (3D) photoresist (PR) profile using the photomask, illumination conditions, and a PR development model. The 3D PR profile is fed into the feature model, Papaya, as the initial PR etch mask condition. The study of the cumulative effect of the gate etch process required to transfer a photomask layout into a gate stack allows for a better understanding of the impact one step in the gate etch process can have on subsequent steps in the process. Studies of pattern transfer of a SRAM bit cell into a gate stack have shown that more edge movement occurs at line ends than at line sides. The line ends are more exposed to incoming etchants and have less opportunity for passivant buildup from the etching wafer than along line sides. An increase in sidewall slope at line ends during the trim and HM etch is observed experimentally and predicted by the model. The slope at line ends during trim and HM etch is more prevalent for narrow ends versus the wider “contact” ends. The lower the PR etch mask height after the HM etch step, the larger the angle seen at line ends which increases the line end pullback. So, a correlation exists between higher wafer power during the HM etch and line end pullback. Passivant formation at the polysilicon sidewall during the main etch/soft landing/overetch polysilicon etch sequence can straighten the profile as well as cause hourglassing and trapezoidal profiles. Passivant thickness, passivant deposition rate, as well as the passivant to polysilicon etch ratio all control this profile behavior. Increased passivation levels also have the tendency to increase linewidth roughness. In FinFET manufacture the gate etch needs to account for the increased topography introduced by the fins.