Gate etch process model for static random access memory bit cell and FinFET construction

Abstract

A reactor/feature/lithography modeling suite has been developed to study the gate etch process. The gate etch process study consists of an eight step process designed to etch through a hard mask (HM)/antireflective coating/polysilicon gate stack and a 22+ step modeled process for FinFET (field effect transistor) manufacture. Coupling to a lithography model allows for a study of how a static random access memory (SRAM) bit cell layout transfers into the gate stack during the gate etch process. The lithography model calculates a three-dimensional (3D) photoresist (PR) profile using the photomask, illumination conditions, and a PR development model. The 3D PR profile is fed into the feature model, Papaya, as the initial PR etch mask condition. The study of the cumulative effect of the gate etch process required to transfer a photomask layout into a gate stack allows for a better understanding of the impact one step in the gate etch process can have on subsequent steps in the process. Studies of pattern transfer of a SRAM bit cell into a gate stack have shown that more edge movement occurs at line ends than at line sides. The line ends are more exposed to incoming etchants and have less opportunity for passivant buildup from the etching wafer than along line sides. An increase in sidewall slope at line ends during the trim and HM etch is observed experimentally and predicted by the model. The slope at line ends during trim and HM etch is more prevalent for narrow ends versus the wider “contact” ends. The lower the PR etch mask height after the HM etch step, the larger the angle seen at line ends which increases the line end pullback. So, a correlation exists between higher wafer power during the HM etch and line end pullback. Passivant formation at the polysilicon sidewall during the main etch/soft landing/overetch polysilicon etch sequence can straighten the profile as well as cause hourglassing and trapezoidal profiles. Passivant thickness, passivant deposition rate, as well as the passivant to polysilicon etch ratio all control this profile behavior. Increased passivation levels also have the tendency to increase linewidth roughness. In FinFET manufacture the gate etch needs to account for the increased topography introduced by the fins.