Investigating the Impact of Schmitt Trigger on SRAM Cells at 32 nm Technology Node for Low Voltage Applications

Abstract

In this paper Schmitt trigger based three different static random access memory bit cells–7, 9 and 10 T–are designed at a 32 nm technology node and their results are analyzed. The static noise margin obtained for 7, 9, and 10 T SRAM bit cells for hold operation are–22, 131, and 126 mV respectively. While, for the read operation the noise margin values are–22, 131, and 27 mV respectively. The dynamic write analysis reveals that the 9 T SRAM cell has a minimal pulse width requirement of 35 ns for a successful write operation. These cache memories are subject to temperature variation operation. Therefore, the Schmitt trigger based bit cells are analyzed by varying temperatures from −10 to 110 ℃. The temperature variation analysis demonstrates 10 T SRAM cell has the least variation in static performance. Another parameter used to compare the performance of the cells is leakage current. This identifies 9 T SRAM bit cell has the maximum leakage current with 635 pA and 630 pA for Q = ‘0’ and ‘1’ respectively.