Static Frequency Divider Research Articles

An ultra-high-speed ECL-BiCMOS technology with silicon fillet self-aligned contacts

We have developed a half-micron super self-aligned BiCMOS technology for high speed application. A new SIlicon Fillet self-aligned conTact (SIFT) process is integrated in this BiCMOS technology enabling high speed performances for both CMOS and ECL bipolar circuits. In this paper, we describe the process design, device characteristics and circuit performance of this BiCMOS technology. The minimum CMOS gate delay is 38 ps on 0.5 /spl mu/m gate and 50 ps on 0.6 /spl mu/m gate ring oscillators at 5 V. Bipolar ECL gate delay is 24 ps on 0.6 /spl mu/m emitter ring oscillators with collector current density of 40 kA/cm/sup 2/. A single phase decision circuit operating error free over 8 Gb/s and a static frequency divider operating at 13.5 GHz is demonstrated in our BiCMOS technology. >

GaInP/GaAs HBTs for high-speed integrated circuit applications

The use of GaInP/GaAs heterojunction bipolar transistors (HBTs) for integrated circuit applications is demonstrated. The discrete devices fabricated showed excellent DC characteristics with low V/sub ce/ offset voltage and very low temperature sensitivity of the current gain. For a non-self-aligned device with a 3- mu m*1.4- mu m emitter area, f/sub T/ was extrapolated to 45 GHz and f/sub max/ was extrapolated to 70 GHz. The measured 1/f noise level was 20 dB better than that of AlGaAs HBTs and comparable to that of low-noise silicon bipolar junction transistors, and the noise bump (Lorentzian component) was not observed. The fabricated gain block circuits showed 8.5 dB gain with a 3-dB bandwidth of 12 GHz, and static frequency dividers (divide by 4) were operable up to 8 GHz.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Static frequency dividers for high operating speed (25 GHz, 170 mW) and low power consumption (16 GHz, 8 mW) in selective epitaxial Si bipolar technology

Static frequency dividers have been fabricated in a selective epitaxial bipolar technology using 0.8 mu m lithography. The measured maximum frequency of 25 GHz is the highest value reported for static silicon dividers. Moreover, a 16 GHz low-power version is presented which consumes only 8 mW in the first stage.

39.5-GHz static frequency divider implemented in AlInAs/GaInAs HBT technology

A static divide-by-4 frequency divider operating at 39.5 GHz with a corresponding gate delay of 12.6 ps was implemented using InP-based HBT technology. The AlInAs/GaInAs HBT devices utilized in the divider incorporated a graded emitter-base (E-B) junction and had a unity gain cutoff frequency, maximum frequency of oscillation, and current gain beta of 130 GHz, 91 GHz, and 39, respectively. The divider was operated with a 3-V power supply and consumed a total power of 425 mW (77 mW per flip-flop). The divider functional yield was over 90%. The operating frequency of this circuit is the highest ever reported for a static divider.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A Si bipolar 28-GHz dynamic frequency divider

A dynamic frequency divider applying the regenerative frequency division principle has been developed. A spiral inductor on the silicon substrate used as a load is characterized, and an improved one-port model with the substrate resistance is discussed. A 1/16 frequency divider was implemented with a silicon bipolar technology with a cutoff frequency of 40 GHz. The operation frequency range was 11.8-28.1 GHz, covering the Ka band (18-26.5 GHz). The inductive load has improved the maximum operation frequency by 7%, compared with a conventional circuit. Complemented with a 21-GHz static frequency divider previously reported by the authors, the whole microwave frequency range up to 26.5 GHz has been completely covered with the silicon bipolar technology. The maximum operation frequency of a silicon MMIC has been extended to the millimeter-wave frequency region for the first time. >

1 GHz CMOS 1/8 static frequency divider operating at 1V

A CMOS divide-by-eight static frequency divider operating at 1.0 GHz and dissipating only 1.7mW at a supply voltage of 1.0 V is described. The corresponding power and power-delay products for the first stage toggle-type flipflop (T-F/F) are 0.32mW and 0.32 pJ, which are the best yet reported for any CMOS flipflop. The divider owes its high performance to 0.2 μm gate CMOS process technology and a new differential static T-F/F circuit. This divider is particularly suitable for dividing communication band frequencies in the front end of a battery-operated wireless hand-held terminal for personal communication.

36-GHz static digital frequency dividers in AlInAs-GaInAs HBT technology

Static divide-by-four circuits have been fabricated that operate up to 36 GHz using AlInAs-GaInAs heterojunction bipolar transistor (HBT) IC technology processing an f/sub t/ and f/sub max/ of 110 and 73 GHz, respectively. The transistors used consisted of an abrupt emitter-base junction design which incorporated a low-temperature p-GaInAs spacer as part of the base to inhibit beryllium diffusion. The AlInAs-GaInAs HBT device layers were grown lattice-matched to semi-insulating InP substrates by solid-source molecular beam epitaxy (MBE).

A Si bipolar 21-GHz/320-mW static frequency divider

A silicon bipolar divide-by-eight static frequency divider was developed. A state-of-the-art advanced borosilicate-glass self-aligned (A-BSA) transistor technology that has a cutoff frequency of 40 GHz at V/sub ce/=1 V was applied. Optimum circuit and layout designs were carried out for high-speed/low-power operation. The single-ended input realized by an on-chip metal-insulator-metal (MIM) capacitor makes it easy to use in microwave applications. Ultrahigh-speed operation, up to 21 GHz, was realized, with 320-mW power dissipation from a single +5-V supply. The static frequency divider is a suitable prescaler for phase-locked oscillators (PLOs), completely covering microwave frequencies from L band through Ku band (1-18 GHz).< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Analysis of highly doped collector transistors by using two-dimensional process/device simulation and its application of ECL circuits

A report is presented of the results of an investigation of device parameters and collector-to-emitter breakdown voltages of double polysilicon self-aligned transistors with highly doped collectors using a two-dimensional process/device simulation system. Favourable phosphorous-ion implanting condition for a highly doped pedestal collector was found to achieve a high cutoff frequency as well as low AC base resistance and small base-collector capacitance, thereby keeping the minimum collector-to-emitter breakdown voltage of 3 V. The authors also report ECL circuit performance improvements achieved in experiments that realized a minimum ECL gate delay time of 26.3 ps/gate at switching current of 1.64 mA as a result of process optimization. Moreover, a 1/8 static frequency divider T-F/F has been observed to operate up to a maximum frequency of 15.8 GHz.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

14 GHz low-power highly sensitive static frequency divider using quantum well AlGaAs/GaAs/AlGaAs FET technology

A 14 GHz static frequency divider has been fabricated using an enhancement/depletion 0.3 mu m recessed-gate AlGaAs/GaAs/AlGaAs quantum well FET process. The divider has a power dissipation of 35 mW at a supply voltage of 1.80 V. The minimum input power for dividing operation is 8.3 dBm at a maximum input frequency of 14.2 GHz, which is lowered to -6.2 dBm, when operating at 12.0 GHz. >

An analytical maximum toggle frequency expression and its application to optimizing high-speed ECL frequency dividers

A novel method is used to analyze static and regenerative frequency dividers by relating their performance to that of the constituent EXCLUSIVE-OR (XOR) gates. It is found that the behavior of the propagation delay of XOR gates is quite linear, and this allows the derivation of a propagation delay expression for XOR gates using a sensitivity analysis. The validity of the expression is checked by comparison with SPICE simulations and with results from the literature, and agreement to 10% is obtained. It has been found that this expression can be used to accurately predict the maximum toggle frequency of frequency dividers. Using this expression, it has also been verified that the maximum toggle frequency of regenerative frequency dividers is about twice as high as that of static frequency dividers. In order to optimize frequency dividers, figures of merit for frequency dividers realized in silicon and AlGaAs-GaAs technologies are proposed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Self-aligned AlInAs-GaInAs heterojunction bipolar transistors and circuits

AlInAs-GaInAs heterojunction bipolar transistors (HBTs) and static flip-flop frequency dividers have been fabricated. An f/sub t/ and an f/sub max/ of 49 and 62 GHz, respectively, have been achieved in a device with a 2*5- mu m/sup 2/ emitter. Current-mode logic (CML) was used to implement static divide-by-two and divide-by-four circuits. The divide-by-two circuit operated at 15 GHz with 82-mW power dissipation for the single flip-flop. The divide-by-four circuit operated at 14.5 GHz with a total chip power dissipation of 444 mW.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Low-temperature buffer GaAs MESFET technology for high-speed integrated circuit applications

The fabrication of high-performance digital integrated circuits with low-temperature buffer (LTB) GaAs MESFET technology is presented. Individual 0.2- mu m-gate-length transistors show a g/sub m/ of 600 mS/mm and an extrapolated f/sub T/ of 80 GHz. Backgating and light sensitivity are eliminated with the LTB technology. Static source-coupled FET logic frequency dividers exhibit a maximum clock rate of 22 GHz.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A submicrometer high-performance bipolar technology

The description of a submicrometer self-aligned bipolar technology developed to minimize the device topography and to provide shallow profiles for high-performance (ECL) emitter-coupled logic applications is presented. The technology features 0.8- mu m design rules, planar beakless field oxide, polysilicon-filled deep trench isolation, and the use of rapid thermal annealing (RTA). Conventional ECL circuits with 35-ps gate delays, a novel AC-coupled active-pull-down (API) ECL circuit with 21-ps gate delay, and a 1/128 static frequency divider operated at a maximum clocking frequency of 12.5 GHz are demonstrated. >

A 1- mu m polysilicon self-aligning bipolar process for low-power high-speed integrated circuits

A double-poly-Si self-aligning bipolar process employing 1- mu m lithography is developed for very-high-speed circuit applications. Epilayer doping and thickness are optimized for breakdown voltages and good speed-power performance. Shallow base-emitter profiles are obtained by combining low-energy boron implantation and rapid thermal annealing (RTA) for the emitter drive-in. A transit frequency f/sub T/=14 GHz at V/sub BC/=-1 V and a current-mode-logic (CML) gate delay of 43 ps at 30 fJ are achieved. For an emitter size of 1.0*2.0 mu m/sup 2/ a minimum power-delay product of 15 fJ is calculated. Circuit performance capability is demonstrated by a static frequency divider operating up to 15 GHz.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

High-speed DCFL circuits with very shallow junction GaAs JFETs

High-speed DCFL (direct-coupled FET logic) circuits implemented with advanced GaAs enhancement-mode J-FETs are discussed. A divide-by-four static frequency divider operates at up to 6 GHz with a power consumption of 20 mW/flip-flop. A high channel concentration of more than 1*10/sup 18/ cm/sup -3/ together with a very shallow junction depth of less than 30 nm for the p/sup +/-gate results in a transconductance as high as 340 mS/mm at a gate length of 0.8 mu m. Open-tube diffusion of Zn using diethylzinc and arsine makes it possible to control a very shallow p/sup +/-layer less than 10 nm thick. The propagation delay time, as measured with a ring oscillator, was 22 ps/gate with a power consumption of 0.42 mW/gate.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Submicrometer n/sup +/-Ge gate AlGaAs/GaAs MISFETs

Submicrometer n/sup +/-Ge gate AlGaAs/GaAs MISFETs have been developed by designing a fabrication process for the n/sup +/-implanted region. The short-channel effect was sufficiently suppressed by lowering the ion-implantation energy down to 50 keV to achieve a standard deviation of threshold voltage as small as 13 mV for 0.5- mu m-gate FETs in a 2-in-diameter wafer. The source resistance was reduced by increasing the annealing temperature to 850 degrees C to obtain a transconductance of 500 mS/mm for a 0.5- mu m-gate FET. Even after annealing at such a high temperature, the quality of the channel layer was maintained at a sufficient level to realize a large cutoff frequency of 70 GHz for a 0.4- mu m-gate FET. A divide-by-four static frequency divider was also fabricated using the above-mentioned fabrication technology. Successful operation at 16 GHz at 300 K was obtained with a divider using 0.9- mu m-gate FETs at a low power dissipation of 36 mW per T-flip-flop. >

0.15 μm GaAs MESFETs applied to ultrahigh-speed static frequency dividers

0.15 μm gate-length FETs fabricated by SAINT using photolithography are applied to ultrahigh-speed static frequency dividers. Short channel effects are suppressed by a buried p-layer and shallow active layers formed by low energy implantations and rapid thermal annealing. The maximum cutoff frequency of the 0.15 μm gate-length FETs was 80.6 GHz. The maximum toggle frequency of the LSCFL one-quarter frequency divider is 26.8 GHz with a power dissipation of 263 mW.

Ultra-high-speed digital circuit performance in 0.2- mu m gate-length AlInAs/GaInAs HEMT technology

The fabrication of fifteen-stage ring oscillators and static flip-flop frequency dividers with 0.2- mu m gate-length AlInAs/GaInAs HEMT technology is described. The fabricated HEMT devices within the circuits demonstrated a g/sub m/ transconductance of 750 mS/mm and a full-channel current of 850 mA/mm. The measured cutoff frequency of the device is 120 GHz. The shortest gate delay measured for buffered-FET-logic (BFL) ring oscillators at 300 K was 9.3 ps at 66.7 mW/gate (fan-out=1); fan-out sensitivity was 1.5 ps per fanout. The shortest gate delay measured for capacitively enhanced logic (CEL) ring oscillators at 300 K was 6.0 ps at 23.8 mW/gate (fan-out=1) with a fan-out sensitivity of 2.7 ps per fan-out. The CEL gate delay reduced to less than 5.0 ps with 11.35-mW power dissipation when measured at 77 K. The highest operating frequency for the static dividers was 26.7 GHz at 73.1 mW and 300 K.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A 20-GHz frequency divider implemented with heterojunction bipolar transistors

This paper reports a high-speed frequency divider implemented with AlGaAs/InGaAs/GaAs heterojunction bipolar transistors (HBT's). The divide-by-four static frequency divider was fabricated with a fully self-aligned dual-lift-off HBT process. A maximum operating frequency of 20.1 GHz was achieved. This is the highest frequency ever reported for static frequency dividers.