Abstract
The description of a submicrometer self-aligned bipolar technology developed to minimize the device topography and to provide shallow profiles for high-performance (ECL) emitter-coupled logic applications is presented. The technology features 0.8- mu m design rules, planar beakless field oxide, polysilicon-filled deep trench isolation, and the use of rapid thermal annealing (RTA). Conventional ECL circuits with 35-ps gate delays, a novel AC-coupled active-pull-down (API) ECL circuit with 21-ps gate delay, and a 1/128 static frequency divider operated at a maximum clocking frequency of 12.5 GHz are demonstrated. >
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