Static Complementary Metal Oxide Semiconductor Research Articles

A Comprehensive Review of Power Consumption in Digital Logic Circuits at Ultra-Low Subthreshold CMOS Levels

In the anticipated spectrum, a lot of work has gone into managing the trade-offs between power, location, and efficiency in the moderate efficiency, moderate power region. However, research into the extremities of this spectrum remains restricted. In particular, there hasn't been enough research done on the extremes of extraordinarily low power consumption with appropriate efficiency and extraordinary efficiency with energy that is within realistic bounds. In this work, very low subthreshold power levels are used to study the power consumption characteristics of digital logic circuits in static Complementary Metal-Oxide-Semiconductor (CMOS) devices. The study shows that operating transistors below their threshold voltage might result in significant energy savings. This research emphasises the significance of subthreshold design strategies for contemporary electronic circuits that aspire for low-power operation without sacrificing efficiency. The results highlight the potential for significant progress in energy-efficient circuit design and highlight the delicate balance between preserving performance and cutting power usage. As a result, this research adds to our understanding of low-power electronics and provides information that may lead to the development of future technologies that are more efficient and sustainable. Keywords— Power consumption analysis, Digital logic circuits, Ultra-low power, Subthreshold operation, Static CMOS gates

A methodology of designing and optimising a 4-bit absolute-value detector for the application of Brain-computer Interface

Digital integrated circuits perform logical operations through several modules composed of logic gates. As a common module in digital circuits, the absolute value detector is applied to compare the absolute value of two binary inputs and can be further used for data sorting and searching. In clinical medicine, the detector can receive biological data from the sensor and control the instrument on the operating table. A typical application is Brain-computer Interface (BCI). Therefore, the performance of detectors is significant to electronic devices like computers. The optimisation of detectors usually concentrates on their propagation delay and power consumption. But theoretical optimisation will inevitably use simple logic and have large fan-in, and it is difficult to be implemented in practice. Here we explore an alternative plan that is more convenient to be produced in the industry, which combines static complementary metal-oxide semiconductor (CMOS) technology and transmission gates. After gate sizing, the critical path calculates the propagation delay and energy based on the logical effort theory. Finally, the relationship between energy and delay is analysed by scaling the voltage supply and the minimum energy occurs when the delay grows to 1.5 times the minimum delay.

A low power design using FinFET based adiabatic switching principle: Application to 16-Bit arithmetic logic unit

This paper presents a novel 16-bit arithmetic logic unit (ALU) design by cascading simple 1-bit ALUs using metal–oxide-semiconductor field effect transistor (MOSFET) and FinFET technologies while incorporating adiabatic switching principle. Analyses are carried out at 32 nm Berkley predictive technology module (PTM). The paper has employed popular standard adiabatic logic families– such as quasi-static energy recovery logic (QSERL), two phase drive adiabatic dynamic complementary metal oxide semiconductor (CMOS) logic (2PADCL), adiabatic dynamic CMOS logic (ADCL), and two phase clocked adiabatic static CMOS logic (2PASCL). Single-phase adiabatic logic circuit is also introduced. Results show that the proposed technique has power savings of 67.14 %, 39.47 %, 34.65 %, 8.73 %, and 4.16 % for CMOS, QSERL, 2PADCL, ADCL, and 2PASCL respectively with MOSFET technology whereas, it saves 95.22 %, 21.34 %, 20.75 %, 15.66 %, and 8.69 % respectively for same literatures with FinFET technology.

A power efficient fully adiabatic logic circuit design approach: application to inverter and 8421 to excess-3 code converter

Decreasing power consumption is the leading challenge for very-large-scale-integrated (VLSI) designers. This paper introduces an innovative prototype for a power-efficient standard or a fully-adiabatic binary-coded-decimal (BCD) 8421 to Excess-3 (XS-3) code converter. The proposed design is compared with traditional complementary metal oxide semiconductor (CMOS) as well as two popular fully adiabatic logic families: adiabatic dynamic CMOS logic (ADCL) and two phase clocked adiabatic static CMOS logic (2PASCL). This investigation was conducted at frequencies ranging from 100 to 900 MHz. The circuit employs 0.3 μm CMOS technology, with channel length and width set at 0.3 μm and 0.75 μm, respectively. The power savings for the proposed logic at 500 MHz when compared to standard CMOS logic, ADCL, and 2PASCL are 54.54%, 28.57%, and 16.67%, respectively.

Energy-Efficient circuits with improved diode free adiabatic logic design methodology

This paper demonstrates a detailed analysis of an unique improved diode-free adiabatic logic (IDFAL) circuit. The IDFAL is operated based on adiabatic switching principle. To indicate the circuit effectiveness, numerous analyses are carried out on different complementary metal oxide semiconductor (CMOS) technology nodes. Logic circuits, viz., NOT and NAND are analyzed and simulated using the traditional CMOS design style and some popular adiabatic logic design techniques: two-phase clocked adiabatic static CMOS logic (2PASCL), diode free adiabatic logic (DFAL), adiabatic dynamic CMOS logic (ADCL), two-phase adiabatic dynamic CMOS logic (2PADCL), quasi-static energy recovery logic (QSERL), and clocked CMOS adiabatic logic (CCAL). The results are compared with the proposed design (IDFAL) at various operating frequencies. The results revealed that the IDFAL inverter circuit has the least power delay product (PDP) among the reported adiabatic design methodologies and saves 91.59 % over the counter-part CMOS inverter at 16 nm high-performance predictive technologies (HP_PTM).

Transistor Count Reduction Technique for Clockfree Null-convention Arithmetic Logic Circuits

Null Convention Logic (NCL) is a robust clock-less technique for designing asynchronous delay-insensitive circuits. The traditional complementary metal oxide semiconductor (CMOS) approach is often used for designing NCL circuits, which tends to occupy a large area. To address this issue, a low power design technique Gate Diffusion Input (GDI) is introduced for designing the NCL circuits. This GDI design methodology is the promising alternative for the static CMOS designs, which allows the reduction in area and power consumption while maintaining the low complexity of the logic design. In this paper, a novel GDI based NCL designs are proposed and designed. However, the voltage swings in the GDI approach leads to the considerable amount of voltage drop at the output. This limitation is addressed by using low threshold transistors where a voltage drop is expected, and high threshold transistors are used for the regenerative inverters at the output. The proposed approach has been verified by designing the NCL Ripple Carry Adder (RCA), Unpipelined multiplier, pipelined multiplier and Unpipelined ALU by using the GDI technique. These models are designed and simulated using Cadence Virtuoso and an average of 13.5 % reduction in the transistor count is observed for these GDI based NCL models when compared to the CMOS models.

LAHAF: Low-power, area-efficient, and high-performance approximate full adder based on static CMOS

In this article, a low power, area-efficient full adder cell designed with approximate outputs is presented. The static Complementary Metal Oxide Semiconductor (CMOS) structure is applied to design this approximate full adder energy efficient (up to 72% improvement). The proposed cell simulated in HSPICE with 32nm CMOS technology in four different scenarios. First, the proposed cell was assessed as a 1-bit full adder cell; second, the proposed cell applied in a 4-bit carry ripple adder structure. In the third and fourth scenarios, the proposed cell's power consumption and performance were assessed in different power supply voltages, temperatures, and a larger load capacitor. Approximate computing is a design paradigm that is applicable in image processing as an error-resilient application. MATLAB exploited to assess the proposed approximate full adder in image addition application in three different scenarios. The outputs evaluated by different image quality metrics (such as peak signal to noise ratio (PSNR)) and the final outputs of approximation are acceptable in this application due to image quality metrics.

A novel ultra-low power 7T full adder design using mixed logic

The key point is to design and implementation of the full adder which provides high-speed, Power efficiency and leas area with good voltage swing”.Where the term ‘Novel’ indicates that If something is so new, genuine and original that it had never been seen, used or even thought of before, call it is considered as ‘novel’ and ‘Ultra low power’ indicates that with the minimal amount of system power is enough for performing the respective operation of its own. In this article, a new High Performance and low power full adder utilizing a distinctive design "Mixed Logic Design" is recommended in implementation. The mixed - logic design combines Modified Gate diffusion input (MGDI) Transmission Gate Logic (TGL), Static CMOS logic, Pass transistor logic(PTL )and various logics which requires the recommended circuit. Full adder is a digital circuit which performs the sum of bits. In many PC’s and various kinds of microprocessors, adders are utilized in the ALU. The traditional Complementary Metal Oxide Semiconductor (CMOS) Full adder consisting of 28-Transistors and is built on a traditional Complementary Metal Oxide Semiconductor structure. GDI technique is low power and high-speed design technique where it takes 10 T.Gate Diffusion Input is one of the circuit design logics which occupies less area, simulates with high speed and power-efficient technique. It entails less count of transistors as correlated to traditional Complementary Metal Oxide Semiconductor technology. But the disadvantage with Gate Diffusion Input technique is that it provides an output having poor logic swing after simulation. The Modified-Gate diffusion input (MGDI ) technique rectifies this issue by implementing FA with 8T.But we are implementing another alternative “Mixed logic design” (combining the GDI, CMOS, TGL, etc logics ) and designing the Circuit with least count of transistors and compare with other unique logics which helps them to simulate the circuit in a power-efficient way and time delay.

Novel Low-Complexity and Low-Power Flip-Flop Design

In this paper, a compact and low-power true single-phase flip-flop (FF) design with fully static operations is presented. The design is developed by using various circuit-reduction schemes and features a hybrid logic style employing both pass transistor logic (PTL) and static complementary metal-oxide semiconductor (CMOS) logic to reduce circuit complexity. These circuit optimization measures pay off in various aspects, including smaller clock-to-Q (CQ) delay, lower average power, lower leakage power, and smaller layout area; and the transistor-count is only 17. Fabricated in TSMC 180 nm CMOS technology, it reduces by over 29% the chip area compared to the conventional transmission gate FF (TGFF). To further show digital circuit/system level advantages, a multi-mode shift register has been realized. Experimental measurement results at 1.8 V/4 MHz show that, compared with the TGFF design, the proposed design saves 64.7% of power consumption while reducing chip area by 26.2%.

Novel Area-efficient Null Convention Logic based on CMOS and Gate Diffusion Input (GDI) Hybrid

Null convention logic (NCL) is a promising delay insensitive paradigm for constructing asynchronous circuits. Traditionally, NCL circuits are implemented utilizing complementary metal oxide semiconductor (CMOS) technology that has large area overhead. To address this issue, a HYBRID methodology is introduced for realizing NCL circuits in this paper. The proposed approach utilizes both CMOS and gate diffusion input (GDI) techniques to significantly reduce the area. Compared with the conventional static CMOS NCL counterpart, the HYBRID implementation of an NCL up counter demonstrate an average of 10% reduction in the transistor count.

Design and Implementation of Full Adder using Different XOR Gates

A Full Adder is a logical circuit that servers a great part in the design of application particular integrated circuits. It is the basic component found in VLSI and DSP applications. The applications of Full adder in VLSI include ALU design, Address generation in processors, Multipliers and so on. Power consumption is one of the most significant parameters of full adder. Therefore, reducing power consumption in full adder is very important. In this paper, Design XOR gate using Transmission gate logic (TGL), Pass transistor logic (PTL) and Static Complementary metal oxide semiconductor logic (CMOS). Also design Full Adder circuit using different XOR gate designs. These circuits are designed and implemented, simulated using Mentor Graphics Tool. After getting simulation results, compare the different XOR gate designs based full adders in terms of power consumption and delay. Using the comparative analysis for the designed Full Adders, an effective adder design can be chosen based on the performance criteria as required by the designer.

Charge balancing symmetric pre‐resolve adiabatic logic against power analysis attacks

A novel, energy efficient and power analysis robust logic style called the charge balancing symmetric pre-resolve adiabatic logic (CBSPAL) is proposed to overcome the susceptibility of cryptosystems against side channel power analysis attacks. It employs differential cascode logic tree structure with a pre-resolving feature, which realises improved energy efficiency by minimising non-adiabatic loss and leakage current. The energy efficiency of the proposed logic against static complementary metal oxide semiconductor (CMOS) and other existing secure adiabatic logic styles is proved. Energy deviation for the different input transitions of the individual logic gates, namely, buffer/NOT, AND/NAND and XOR/XNOR is found to be very minimal and it validates the immunity of the proposed logic against power analysis attacks. SPICE simulation of 4-bit add-round structure implementation using CBSPAL shows an energy saving of 89.5% compared to static CMOS implementation at a frequency of 125 MHz. Security of the proposed logic against the side channel power analysis attack is demonstrated by performing the correlation power analysis attacks as applicable for the SPICE simulations. Exhaustive SPICE simulations have been performed using the 32 nm CMOS predictive technology model libraries.

A Novel Domino Logic with Modified Keeper in 16nm CMOS Technology

Domino logic is a clocked CMOS (Complementary Metal-Oxide Semiconductor) logic with fewer transistors than static CMOS logic. A PMOS (P-type Metal-Oxide Semiconductor) transistor, known as “keeper”, is included in the design to improve the noise tolerance performance and to reduce the leakage current. The aspect ratio i.e. W/L of the keeper (W=width and L=length) is kept low for the correct functionality of the domino logic. This paper proposes a domino logic with modified keeper in order to improve the circuit with respect to power and area as compared to various existing techniques of domino logic i.e. clock delayed domino logic (CDD), high speed domino logic (HSD), multi threshold high speed domino logic (MHSD), clock delayed sleep mode domino logic (CDSMD), sleep switch domino logic (SSDD), PMOS only sleep switch domino logic (PSSDD), reduced delay variations domino logic (RDVD) and Foot Driven Stack Transistor Domino Logic (FDSTDL). The proposed as well as existing domino logics, for 8-input as well as 16-input OR gate in 16nm CMOS technology, are simulated for different values of W/L of keeper with W/L ratio ranging from 1 to 6. The power-delay-product(PDP) of proposed design has improved as compared to the existing designs. For 8-input OR gate and W/L=6, PDP had improved to maximum of 99.99% for CDD and minimum of 38.09% for SSDD.

A Novel Compact Multiplicative Inverse Unit of AES for Low Power and Low Area Applications

Objectives: AES(Advanced Encryption Standard) provides strong encrypted information and also it is easy to produce on a miniature die size and consume low power by reducing the number of gates and transistors in the S-box of AES. The main aim of project is to reduce the number of gates in AES S-box to achieve low area and low power. Methods/Analysis: The proposed technique uses the logical level reduction technique to achieve less number of gates by using Boolean logic. The target of the proposed technique is to design the compact multiplicative inverse unit by circuit and gate level implementation in order to achieve low area and low power utilization. The structure of multiplicative inverse unit is reduced by using logical simplification. The simulation is performed by Tanner tool version 14.11 for circuit level implementation based on static complementary metal oxide semiconductor (CMOS) logic. This tool also provides the information about number of transistors utilized and power consumption of both existing and proposed multiplicative inverse unit. Findings/Novelty: Several cryptographic techniques such as Data Encryption Standard (DES), AES(Advanced Encryption Standard), blowfish and RC4 are adopted based on various applications for specific purposes. Among various techniques, AES provides high security with low power and low area utilization. The conventional multiplicative inverse (MI) unit of AES has 50 gates to perform the multiplicative inverse (MI) operation. So it needs more area and power. To overcome this problem, Boolean logic is applied to perform the logical simplification of the proposed multiplicative inverse unit. From that, it reduces from 50 gates to 39 gates than the existing Mt unit. Totally, 11 gates are reduced in the proposed multiplicative inverse unit. Always the area is directly proportional to the power consumption. The power consumption of the proposed circuit is reduced from 45.7mw to 36.7mw.The proposed multiplicative inverse unit offers 22% area reduction and 19.6% power reduction than the existing MI unit. Applications/Improvement: In the proposed multiplicative inverse unit, only 4 XOR gates are used instead of 14 XOR gates to perform the operation and this in turn helps to achieve less area and low power. The proposed multiplicative inverse unit based AES is applied for low area and low power with high security applications. Keywords: AES, Galois Field Arithmetic, Reduced MI Unit, S-Box, Static CMOS and Boolean Logic

A novel high-speed CMOS circuit based on a gang of capacitors

ABSTRACTThere is no doubt that complementary metal-oxide semiconductor (CMOS) circuits with wide fan-in suffers from the relatively sluggish operation. In this paper, a circuit that contains a gang of capacitors sharing their charge with each other is proposed as an alternative to long N-channel MOS and P-channel MOS stacks. The proposed scheme is investigated quantitatively and verified by simulation using the 45-nm CMOS technology with VDD = 1 V. The time delay, area and power consumption of the proposed scheme are investigated and compared with the conventional static CMOS logic circuit. It is verified that the proposed scheme achieves 52% saving in the average propagation delay for eight inputs and that it has a smaller area compared to the conventional CMOS logic when the number of inputs exceeds three and a smaller power consumption for a number of inputs exceeding two. The impacts of process variations, component mismatches and technology scaling on the proposed scheme are also investigated.

Design of Low-Power High-Performance 2–4 and 4–16 Mixed-Logic Line Decoders

This brief introduces a mixed-logic design method for line decoders, combining transmission gate logic, pass transistor dual-value logic, and static complementary metal-oxide semiconductor (CMOS). Two novel topologies are presented for the 2-4 decoder: a 14-transistor topology aiming on minimizing transistor count and power dissipation and a 15-transistor topology aiming on high power-delay performance. Both normal and inverting decoders are implemented in each case, yielding a total of four new designs. Furthermore, four new 4-16 decoders are designed by using mixed-logic 2-4 predecoders combined with standard CMOS postdecoder. All proposed decoders have full-swinging capability and reduced transistor count compared to their conventional CMOS counterparts. Finally, a variety of comparative spice simulations at 32 nm shows that the proposed circuits present a significant improvement in power and delay, outperforming CMOS in almost all cases.

Performance Analysis of a Low-Power High-Speed Hybrid 1-bit Full Adder Circuit

In this paper, a hybrid 1-bit full adder design employing both complementary metal–oxide–semiconductor (CMOS) logic and transmission gate logic is reported. The design was first implemented for 1 bit and then extended for 32 bit also. The circuit was implemented using Cadence Virtuoso tools in 180-and 90-nm technology. Performance parameters such as power, delay, and layout area were compared with the existing designs such as complementary pass-transistor logic, transmission gate adder, transmission function adder, hybrid pass-logic with static CMOS output drive full adder, and so on. For 1.8-V supply at 180-nm technology, the average power consumption (4.1563 $\mu $ W) was found to be extremely low with moderately low delay (224 ps) resulting from the deliberate incorporation of very weak CMOS inverters coupled with strong transmission gates. Corresponding values of the same were 1.17664 $\mu $ W and 91.3 ps at 90-nm technology operating at 1.2-V supply voltage. The design was further extended for implementing 32-bit full adder also, and was found to be working efficiently with only 5.578-ns (2.45-ns) delay and 112.79- $\mu $ W (53.36- $\mu $ W) power at 180-nm (90-nm) technology for 1.8-V (1.2-V) supply voltage. In comparison with the existing full adder designs, the present implementation was found to offer significant improvement in terms of power and speed.

Optimization of fat tree encoder for ultra high speed analog to digital converter using 45 nanometer technology

The design of high speed, compact and low power fat tree encoder circuits using static CMOS gates is presented. In this paper, we propose a modified 3 bit fat tree encoder (FTE) that can operate in high frequency without a sophisticated circuit structure. In addition, the technique of hardware sharing is adopted in this design to reduce the number of transistors. The study uses complementary metal oxide semiconductor (CMOS) 45nm-technology. The proposed static design has improved delay and power compared to a conventional ROM encoder circuit implementation. The simulation result indicates that it functions successfully and works at 200-MHz speed. The average power consumption of the circuit under room temperature is 20.7nW. The total core area is 0.011mm2. As expected, the proposed design can be easily integrated in various kind of digital application.

High-performance dynamic circuit techniques with improved noise immunity for address decoders

Dynamic circuits are extensively employed in very-large-scale integration chips because of their high performance. Unfortunately, they are more susceptible to noise than static complementary metal oxide semiconductor circuits. With the continuous down-scaling of process technology and the supply voltage, improved noise immunity in dynamic circuits is essential. In this study, two new schemes are proposed to enhance the noise tolerance of dynamic address decoders, and their performance, noise tolerance and power consumption are compared with those of a conventional dynamic decoding circuit and a previous scheme. A dynamic 4–16 decoder employing the proposed delay technique exhibits 131.5 and 2.6% improvements in noise tolerance and performance, respectively, whereas a 4–16 decoder exploiting the proposed mirror scheme achieves 291.2 and 25.2% improvements; both used 65 nm process technology. Moreover, the proposed techniques are more resistant to process variations and more tolerant of a lower power supply.

LSI implementation of a low-power 4×4-bit array two-phase clocked adiabatic static CMOS logic multiplier

As the density and operating speed of complementary metal oxide semiconductor (CMOS) circuits increases, dynamic power dissipation has become a critical concern in the design and development—of personal information systems and large computers. The reduction of supply voltage, node capacitance, and switching activity are common approaches used in conventional CMOS. In adiabatic switching circuits, the current flow through transistors can be significantly reduced by ensuring uniform charge transfer over the entire available time. This paper presents the simulation of this current in two-phase clocked adiabatic static CMOS logic (2PASCL) and conventional CMOS. From the SPICE simulations, at transition frequencies from 1 to 12MHz, a 4×4-bit array 2PASCL multiplier shows a maximum reduction in power dissipation of 77% relative to that of a static CMOS. The measurement results of a 4×4-bit array 2PASCL multiplier demonstrate a 57% reduction compared to a 4×4-bit array two-phase clocked adiabatic dynamic CMOS logic (2PADCL). These results indicate that 2PASCL technology can be advantageous when applied to low-power digital devices operated at low frequencies, such as radio-frequency identification (RFID) tags, smart cards, and sensors.