Charge balancing symmetric pre‐resolve adiabatic logic against power analysis attacks

Abstract

A novel, energy efficient and power analysis robust logic style called the charge balancing symmetric pre-resolve adiabatic logic (CBSPAL) is proposed to overcome the susceptibility of cryptosystems against side channel power analysis attacks. It employs differential cascode logic tree structure with a pre-resolving feature, which realises improved energy efficiency by minimising non-adiabatic loss and leakage current. The energy efficiency of the proposed logic against static complementary metal oxide semiconductor (CMOS) and other existing secure adiabatic logic styles is proved. Energy deviation for the different input transitions of the individual logic gates, namely, buffer/NOT, AND/NAND and XOR/XNOR is found to be very minimal and it validates the immunity of the proposed logic against power analysis attacks. SPICE simulation of 4-bit add-round structure implementation using CBSPAL shows an energy saving of 89.5% compared to static CMOS implementation at a frequency of 125 MHz. Security of the proposed logic against the side channel power analysis attack is demonstrated by performing the correlation power analysis attacks as applicable for the SPICE simulations. Exhaustive SPICE simulations have been performed using the 32 nm CMOS predictive technology model libraries.