Abstract
In this paper, a compact and low-power true single-phase flip-flop (FF) design with fully static operations is presented. The design is developed by using various circuit-reduction schemes and features a hybrid logic style employing both pass transistor logic (PTL) and static complementary metal-oxide semiconductor (CMOS) logic to reduce circuit complexity. These circuit optimization measures pay off in various aspects, including smaller clock-to-Q (CQ) delay, lower average power, lower leakage power, and smaller layout area; and the transistor-count is only 17. Fabricated in TSMC 180 nm CMOS technology, it reduces by over 29% the chip area compared to the conventional transmission gate FF (TGFF). To further show digital circuit/system level advantages, a multi-mode shift register has been realized. Experimental measurement results at 1.8 V/4 MHz show that, compared with the TGFF design, the proposed design saves 64.7% of power consumption while reducing chip area by 26.2%.
Highlights
With the growth of the Internet of Things (IoT) and wearable devices, the need for ultra-low power consumption SOC chips is increasing [1]
FFs account for 40% of the chip area and 30% of the total power consumption [4]
FF design is critical to the power consumption performance of the system design and has a significant impact on chip area
Summary
With the growth of the Internet of Things (IoT) and wearable devices, the need for ultra-low power consumption SOC chips is increasing [1]. In an ARM Cortex-M0 processor with minimum instruction and data memories, they are synthesized from standard cells for IoT applications In this design, FFs account for 40% of the chip area and 30% of the total power consumption [4]. There is considerable dynamic power consumption even when the input data signal switching activity is zero or low Basic idea is mitigating the(TSPC)-based load capacitance clock signal by using logic and power circuit. A novel SR latch-based FF using hybrid logic circuit scheme is exhibits a lowest transistor-count a shorter critical path the when compared with previous.
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