Standard Circuit Research Articles

Circuit model for thermoviscous propagation in annular waveguides.

This paper presents a circuit model of the thermoviscous acoustic wave propagation in waveguides with annular cross section. The model, validated against finite element method simulations of the input acoustic impedance, captures the annular waveguide behavior with good accuracy within a frequency bandwidth consistent with the lumped-element approximation. The cascading of multiple circuit models easily allows extending the bandwidth while preserving the same accuracy. The circuit model was derived from the low reduced frequency (LRF) wave propagation model in rectangular layers, representing a valid approximation of the complex LRF solution in annular waveguides. The simplified analytical description allows for the formulation of a compact T-network model comprised of standard circuit elements. This circuit model can be implemented in circuit simulators to accelerate both the analysis and engineering of devices having elements with annular cross section, such as micro-electro-mechanical systems devices or microphones.

Создание поведенческой модели LDMOS транзистора на основе искусственной MLP нейросети и ее описание на языке Verilog-A

The article deals with the creation of a behavioral model of lateral metal oxide transistors (LDMOS) based on a neural network of the multilayer percep-tron type. The model is identified using a backpropa-gation algorithm. Demonstrated the process of creating an ANN model using Pytorch, a machine learning framework for the Python language, with subsequent transfer to the standard analog circuit modeling lan-guage Verilog-A.

Mapping Neural Circuit Biotypes to Symptoms and Behavioral Dimensions of Depression and Anxiety

BackgroundDespite tremendous advances in characterizing human neural circuits that govern emotional and cognitive functions impaired in depression and anxiety, we lack a circuit-based taxonomy for depression and anxiety that captures transdiagnostic heterogeneity and informs clinical decision making. MethodsWe developed and tested a novel system for quantifying 6 brain circuits reproducibly and at the individual patient level. We implemented standardized circuit definitions relative to a healthy reference sample and algorithms to generate circuit clinical scores for the overall circuit and its constituent regions. ResultsIn new data from primary and generalizability samples of depression and anxiety (N = 250), we demonstrated that overall disconnections within task-free salience and default mode circuits map onto symptoms of anxious avoidance, loss of pleasure, threat dysregulation, and negative emotional biases—core characteristics that transcend diagnoses—and poorer daily function. Regional dysfunctions within task-evoked cognitive control and affective circuits may implicate symptoms of cognitive and valence-congruent emotional functions. Circuit dysfunction scores also distinguished response to antidepressant and behavioral intervention treatments in an independent sample (n = 205). ConclusionsOur findings articulate circuit dimensions that relate to transdiagnostic symptoms across mood and anxiety disorders. Our novel system offers a foundation for deploying standardized circuit assessments across research groups, trials, and clinics to advance more precise classifications and treatment targets for psychiatry.

Balancing Straight-line Programs

We show that a context-free grammar of size that produces a single string of length (such a grammar is also called a string straight-line program) can be transformed in linear time into a context-free grammar for of size , whose unique derivation tree has depth . This solves an open problem in the area of grammar-based compression, improves many results in this area, and greatly simplifies many existing constructions. Similar results are shown for two formalisms for grammar-based tree compression: top dags and forest straight-line programs. These balancing results can be all deduced from a single meta-theorem stating that the depth of an algebraic circuit over an algebra with a certain finite base property can be reduced to with the cost of a constant multiplicative size increase. Here, refers to the size of the unfolding (or unravelling) of the circuit. In particular, this results applies to standard arithmetic circuits over (noncommutative) semirings.

Integrated-optics pressure sensor with improved range and sensitivity based on a SiO2 arrayed waveguide grating (AWG) and a 3D printed stereolithography resin module

An integrated optical pressure sensor based on a SiO2 arrayed waveguide grating (AWG) and a phase amplifying pressure block (PAPB) 3D-printed with stereolithography resin is described in this paper. Theoretical analysis of the AWG shows that its sensitivity can be improved by applying pressure on the PAPB instead of the whole chip. This scheme is shown to be feasible by mechanical simulation of a 1 mm-thick SiO2 chip. We use the standard planar lightwave circuit (PLC) process to fabricate a SiO2 AWG and 3D print the PAPB using stereolithography resin SOMOS Imagine 8000. Adding the PAPB module to the AWG chip improves the sensitivity of the sensor by 9 times, and the measuring range reaches 80 MPa. The resolution of the device reaches 0.0007% FS (full scale).

Sequestration of Midazolam, Fentanyl, and Morphine by an Ex Vivo Cardiopulmonary Bypass Circuit.

Cardiopulmonary bypass (CPB) circuits can significantly sequester intravenous anesthetics. Adsorption of medications by our institution's standard circuit (Terumo CAPIOX FX05 oxygenator; noncoated polyvinylchloride tubing) has not been described. We prepared ex vivo CPB circuits with and without oxygenators. Medication combinations studied included midazolam (0.5 mg), fentanyl (50 µg), midazolam (0.5 mg) with morphine (0.5 mg), and midazolam (0.5 mg) with fentanyl (50 µg). Medications were administered after obtaining baseline samples. Samples were drawn at 2, 5, 15, 30, 60, 120, and 180 minutes, and analyzed for concentration of injected medications. Midazolam demonstrated no sequestration after 180 minutes. Fentanyl concentration at 180 minutes was lower with an oxygenator (52.7 ± 12.5 vs. 110.9 ± 12.0 ng/ml, P = 0.00432). More fentanyl was found in solution after 180 minutes when given with midazolam compared to fentanyl given alone in the presence of an oxygenator (101 ± 22.3 vs. 52.7 ± 12.5 ng/ml, P = 0.044). Less midazolam was present after 180 minutes when given with morphine compared to midazolam given alone in the absence of an oxygenator (1264.9 ± 425.6 vs. 2124 ± 254 ng/ml, P = 0.037). We successfully characterized the adsorption of various combinations of midazolam, fentanyl, and morphine to our CPB circuit, showing that fentanyl and midazolam behave differently based on other medications present.

Modelling and Simulation of DC-DC Boost Converter and Inverter for PV System

Research in renewable energy sources has seen an incremental trend for its various advantages over conventional energy sources. Photovoltaic generation system acquires the maximum market share in the energy systems employing the renewable energies. The low efficiency in terms of the output voltage is a prime disadvantage of the photovoltaic generation system. On the other hand, the industries in the majority make use of equipment requiring high voltage input. Considering the requirement of high voltage input for industrial application and the low-voltage constraint of the Photovoltaic (PV) generation system, this paper proposes a modelling and simulation of DC-DC boost converter and three-phase inverter in MATLAB SIMULINK. The circuit is designed based on the traditional standard circuits of the converter and inverter. The investigation resulted the development of an accurate model but also compact compared to other designs. Additionally, this will allow the power electronics circuit simulated beforehand in any experiment-based work.

Fully Three-Dimensional Silicon-Integrated Dielectric Capacitor at 1 µFmm-2 for on-Chip Energy Storage

The increasing request of on-chip energy storage devices is driven by the augmented connectivity between people and things for IoT, portable, and wearable electronic applications. These systems require high performance components with low power consumption, compact size, and high energy storage capability. Supercapacitors (SCs) achieve capacitance density in the order of 0.1–1 mF/mm2. Nonetheless, their poor performance in terms of operation frequency (from Hz to tens of Hz, rarely beyond 1 kHz) and voltage (rarely exceeding 2 V), together with their low compatibility with standard integrated circuit (IC) technologies, have inhibited their integration to date.Dielectric capacitors (DCs) make use of solid-state dielectrics sandwiched between two conductive electrodes. These capacitors operate at high frequency (up to a several MHz) and voltages (exceeding tens of Volt). However, the areal capacitance of DCs is order of magnitude smaller than that of SCs. The use of high dielectric constant materials (k>10) and the exploitation of the third dimension (3D capacitor) to increase the effective surface area of the capacitor per unit volume have been proposed.In this work, we successfully address the challenge of achieving a 3D silicon-based dielectric capacitor with high capacitance density and large operation voltage and frequency range, using a fabrication process that is compatible with silicon ICs technology.Specifically, we report on 3D DCs fully integrated in a silicon chip with areal capacitance up to 1 μF/mm2 by atomic layer deposition of conductive (TiN) and high-k dielectric (Al2O3 and HfAlOX) nanocoatings (20 and 40 nm) into trenches electrochemically etched in silicon with aspect ratio up to 100 [1]. The 3D DCs operate up to 70kHz with an excellent stability with voltage (up to 16V) and temperature (up to 100°C), over 100 h of continuous operation (>108charge/discharge cycles). The 3D DCs exhibit power and energy densities of 566 W/cm2 and 1.7 μWh/cm2, respectively, greater that those of most state-of-the-art dielectric capacitors and supercapacitors.[1] L. M Strambini, A. Paghi, S. Mariani, A. Sood, J. Kalliomäki, P. Järvinen, F. Toia, M. Scurati, M. Morelli, A. Lamperti, G. Barillaro, Three-dimensional silicon-integrated capacitor with unprecedented areal capacitance for on-chip energy storage, Nano Energy, 68, 104281 (2020)

Design and Testing of a Low-Tech DEW Generator for Determining Electromagnetic Immunity of Standard Electronic Circuits

This article describes the effect of high-power electromagnetic environments (HPEMs) on the operation of all basic elements of electrical power networks. Frequency bands are defined for the HPEM environments. Attention is focused particularly on directed energy weapons (DEWs) and intentional electromagnetic interference (IEMI). A classification of DEW and IEMI generators in terms of E-field level and target distance from the DEW or IEMI generator antenna aperture is also described. The main focus of this article is on the design and testing of a low-tech DEW generator used to determine the electromagnetic immunity of standard electronic circuits. In addition, verification of electromagnetic immunity for a simple electronic circuit without adequate protection against the E-field is also explained. The outcome of this article is the determination of the E-field limits for fault-free operation, for malfunctioning states of the tested circuits and for irreversible destruction of the circuits. The measured E-field was compared to basic microwave radiation theory and to simulation results in COMSOL Multiphysics software (COMSOL, Inc. 100 District Avenue Burlington, MA 01803 USA).

Certifying Top-Down Decision-DNNF Compilers

Certifying the output of tools solving complex problems so as to ensure the correctness of the results they provide is of tremendous importance. Despite being widespread for SAT-solvers, this level of exigence has not yet percolated for tools solving more complex tasks, such as model counting or knowledge compilation. In this paper, the focus is laid on a general family of top-down Decision-DNNF compilers. We explain how those compilers can be tweaked so as to output certifiable Decision-DNNF circuits, which are mainly standard Decision-DNNF circuits decorated by annotations serving as certificates. We describe a polynomial-time checker for testing whether a given CNF formula is equivalent or not to a given certifiable Decision-DNNF circuit. Finally, leveraging a modified version of the compiler d4 for generating certifiable Decision-DNNF circuits and an implementation of the checker, we present the results of an empirical evaluation that has been conducted for assessing how large are in practice certifiable Decision-DNNF circuits, and how much time is needed to compute and to check such circuits.

Quench and Stability Modelling of a Metal-Insulation Multi-Double-Pancake High-Temperature-Superconducting Coil

The most detailed, first-principle simulation model of a quench in a high-temperature superconducting metal-insulation multi-module/multi-double-pancake coil, wound with a REBCO coated superconductor/tape and normal-metal tape (co-wind), was developed. It enables one to simulate a normal zone propagation, or non-propagation, in the subtle multi-turn structure of the coil's pancakes due to the inductive coupling and transverse electric contact between all the REBCO turns and co-wind turns along with the external circuit and active and passive quench protection systems. In doing so, the multi-module coil's structure is represented as a “rectilinear equivalent” electric circuit, a branched multi-decker multi-rectangle planar grid, which facilitates the mathematical formulation, using the standard electric circuit differential equations and the Kirchhoff's rules. The transient non-linear comprehensive heat conduction equations are employed to model the thermal part of the phenomenon at the same level of detail. All this turns the model into an effective design tool for metal-insulated, -stabilized and/or -reinforced multi-module coils. A parametric study of quench in a 6-module no-insulation (NI) test coil, using a stainless-steel thin co-wind, was conducted to identify the possibilities of the model. The profound effect of the transverse contact resistivity on an NI-coil quench behavior is confirmed and detailed.

Modeling Funneling Effect With Generalized Devices for SPICE Simulation of Soft Errors

Recent advances in CMOS scaling have made circuits more and more sensitive to errors and dysfunction caused by ionizing radiation, even at ground level, requiring accurate modeling of such effects. Besides generation, transport, and collection of radiation-induced excess carriers, another phenomenon, called funneling, has to be modeled for an accurate prediction of soft errors. The funneling effect occurs when the radiation track crosses a space charge region and generates excess carriers with a density higher than the doping close to it. These carriers distort the electric field of the space charge region, deeply changing the transport mechanism, from diffusion in a field-free semiconductor to drift. The objective of this work is to include funneling as part of the generalized lumped devices model in order to obtain a complete tool for SPICE-compatible simulations of single-event effects (SEEs). The latter approach has been recently proposed to simulate radiation-induced charges in the silicon substrate and is based on the so-called generalized lumped devices that simulate charge generation, propagation, and collection using standard circuit simulators. The generalized devices are here extended to include funneling and used to simulate an alpha particle impinging on the bulk of nMOS and pMOS transistors. The results obtained are validated with TCAD numerical simulations. Finally, an static random-access memory (SRAM) struck by an alpha particle is analyzed. The model predicts that the occurrence of a soft error, i.e., flipping of memory state, may depend on whether or not there is funneling. This justifies the need for accurate modeling of funneling phenomena to predict SEEs in ICs.

Area and power delay product efficient level restored hybrid full adder (LR-HFA)

Full adder circuit is a ubiquitous building block in VLSI systems and application specific integrated circuits. This article presents an area and power delay product (PDP) efficient CMOS based 1 bit full adder which is suitable to perform arithmetic operations. The simulation results obtained for parameter analysis using Cadence tool shows that the proposed adder preserves more than 20.7% power over the conventional CMOS adder. The PDP is reduced by almost 26.8–55.5% and performs 9.8–46.1% faster operation than the existing adders. The proposed design is investigated in terms of variations in supply voltage, load capacitance, process corner and temperature. To evaluate the performance of LR-HFA in real time environment, we embedded it in a 4, 8, 16 bit carry propagation adder. The proposed adder displays improved PDP performance when compared with standard adder circuits.

Realization of Strong CMOS Conforming Full Adder Circuit Using Symmetric Function Lattice Structure

Due to the physical limit that the IC industry may face in the future that transistors size may not be able to shrink anymore,a lot of work had been done to minimize the number of transistors used, instead of shrinking them. One of the highly researched standard circuit to reduce transistor count is the full adder as it appears in almost all computing circuits. In this paper, an alternative to CMOS technology using symmetric Boolean function lattice structure is presented to produce full adder. Symmetric functions are the functions that are invariant under input permutation. Theyhaveaspecialwayofrealizationthat offerssomepossibility to reducethe number oftransistors used. Full adder falls into this classof functions. It has been found that the right full adder lattice structure based circuit only requires 22 transistors to produce the correct function for the sum and c out output. This is a saving of 6 transistors as compared to the standard 28-transistor CMOS full adder. The output delay is around 3.0 ns for the c out output, and around 4.5 ns for the sum output.

Normalization and Correction Factors for Magnetic Tunnel Junction Sensor Performances Comparison

In this manuscript we propose a calculation method where the magneto-resistive elements are modelled as fluctuating resistances to correct the output voltage noise of magnetic tunnel junction (MTJ) from standard electronic circuits. This method is validated on single elements, partial and full Wheatstone bridge circuits, giving rise to a correction factor affecting the output voltage noise as well as sensitivity values. Combining the correction factor and a normalization by the number of MTJs pillars and the pillar surface, we show that the performances extracted by this method allow universal comparison between any results from literature.

Training Spiking Neural Networks in the Strong Coupling Regime.

Recurrent neural networks trained to perform complex tasks can provide insight into the dynamic mechanism that underlies computations performed by cortical circuits. However, due to a large number of unconstrained synaptic connections, the recurrent connectivity that emerges from network training may not be biologically plausible. Therefore, it remains unknown if and how biological neural circuits implement dynamic mechanisms proposed by the models. To narrow this gap, we developed a training scheme that, in addition to achieving learning goals, respects the structural and dynamic properties of a standard cortical circuit model: strongly coupled excitatory-inhibitory spiking neural networks. By preserving the strong mean excitatory and inhibitory coupling of initial networks, we found that most of trained synapses obeyed Dale's law without additional constraints, exhibited large trial-to-trial spiking variability, and operated in inhibition-stabilized regime. We derived analytical estimates on how training and network parameters constrained the changes in mean synaptic strength during training. Our results demonstrate that training recurrent neural networks subject to strong coupling constraints can result in connectivity structure and dynamic regime relevant to cortical circuits.

Comparison of muscle activity while using different input devices in digital pathology

IntroductionThe high prevalence of musculoskeletal disorders in pathologists, together with the current trend towards the digitization of pathology, prompted us to study the different types of input devices employed during the revision of whole slide images, in order to investigate the pattern and extent of muscle activity involved in their use. Material and methodsA comparative study was made of 10 input devices (conventional and vertical mouse, three trackballs, the Ergopointer™, the Rollermouse™, an optical pen mouse, a touchpad, and the Leap Motion™). Six medical students performed a standardized circuit using a Fitts’ Law based tissue array, digitized. The electrical activity of seven upper limb muscles (adductor pollicis, extensor pollicis longus, extensor digitorum, flexor digitorum, middle deltoid, upper trapezius, and middle trapezius) was measured using surface electromyography. ResultsStatistically significant differences in the overall electrical activity among the different input devices, both absolute values in mV as well as normalized values to the upper limb at rest, were observed (p<0.001); the Rollermouse™ (0.1027mV; 139%), Logitech M570 trackball (0.1053mV; 145%), Ergopointer™ (0.1151mV; 167%), conventional mouse (0.1251mV; 191%), and vertical mouse (0.1312mV; 205%) required less activity, while the optical pen mouse (0.1717mV; 299%), Leap Motion™ (0.1803mV; 319%), Expert Mouse trackball (0.1845mV; 329%), EIGIIS trackball (0.2442mV; 468%) and the touchpad (0.2560mV; 496%) required greater muscle mobilization. ConclusionWe designed a system based on Fitts’ Law to compare input devices in digital pathology.Variability between compared devices and muscle activity was found. Long-term use could result in different muscular fatigue patterns.Even though the selection of an input device is a matter of personal preference, its impact on ergonomics should be considered.

The effect of phosphorolcoline-coated cardiopulmonary by-pass circuits on morbidity and mortality in patients with congenital open cardiac surgery

Objective: Our aim in this study is to investigate the relationship between mortality and morbidity of phosphorylcholine coated oxygenator circuit used in heart-lung machine in congenital open heart surgery operations.&#x0D; Materials and Methods: The study was conducted in Dr. Sami Ulus Child Diseases Training and Research Hospital Cardiovascular Surgery Clinic between 2008-2009. 30 congenital heart patients were included. The patients were divided into 2 groups of 15 people. In one of the groups, a phosphorylcholine coated oxygenator circuit was used in the heart lung machine (Group P). In the other group, a standard oxygenator circuit was used (Group C).Congenital heart surgery was performed for 19 Ventricular Septal Defects (VSD), 5 Secundum Atrial Septal Defects (ASD), 3 Primum ASD, 2 Mitral insufficiency and 1 Discret subaortic membrane.&#x0D; Extubation times, intensive care and discharge times, 24-hour drainage follow-up, inotropic drug use, blood and fresh frozen plasma (FFP) transfusion amount, aspartate aminotransferase, alanine aminotransferase, creatine phosphokinase-MB, urea, blood urea nitrogen, creatinine, white cell number of platelets, lactate dehydrogenase, albumin, total protein, C-reactive protein, prothrombin time, partial thromboplastin time, fibrinogen, D-dimer, C5a and elastase levels were compared perioperatively.&#x0D; Results: In the study, it was determined that the discharge time was shorter in Group P. It was found that the increase in d-dimer values with fibrinogen was less in Group P. These were found to be statistically significant (p 0.05). There was no mortality in either group.&#x0D; Conclusion: In this study, phosphorylcholine-coated oxygenator did not significantly reduce the inflammatory response during cardiopulmonary by-pass (CPB). There was no difference between the two groups in terms of morbitidity and mortality.However, the fact that fibrinogen values, which are the acute phase reactants, are lower than the control group and the increase in d-dimer values remain limited may be important in terms of hemocompatibility of the phosphorylcholine coated circuit.

AdaTrust: Combinational Hardware Trojan Detection Through Adaptive Test Pattern Construction

As society becomes increasingly reliant on products and systems that make use of integrated circuits, the defense against potential hardware Trojan attacks by an untrusted foundry becomes an important part of any certification flow for critical components. The slew of recent proposals notwithstanding, a satisfactory solution is still wanting as the solutions offered heretofore either require impractical design/test pattern cost or deliver insufficient detection capabilities, primarily challenged by the noise induced by process variation. The methodology put forth by this proposal aims to remedy this, leveraging an adaptive approach that applies superposition to perform a fine-grained circuit analysis and expose any extant Trojan circuitry. Iterative test pattern modifications, circuit response analysis, and adaptive decision-making are deployed, all embedded within the design-for-test and test pattern cost paradigms of a common industrial circuit. We demonstrate the efficacy of this technique on standard Trust-Hub benchmark circuits with combinational Trojans inserted in sequential designs, showing significant improvement over prior techniques. We also explore the potential cost–benefit tradeoffs that exist within such a methodology, with the intent to provide an efficient solution for an array of potential product markets. This methodology provides a reliable and effective means for Trojan detection, addressing an important piece of the overall circuit certification puzzle.

Discrete-time quantum walk on circular graph: Simulations and effect of gate depth and errors

We investigate the counterparts of random walks in universal quantum computing and their implementation using standard quantum circuits. Quantum walks have been recently well investigated for traversing graphs with certain oracles. We focus our study on traversing a 1D graph, namely a circle, and show how to implement a discrete-time quantum walk in quantum circuits built with universal CNOT and single qubit gates. We review elementary quantum gates and circuit decomposition techniques and propose a generalized version of all CNOT-based circuits of the quantum walk. We simulated these circuits on five different qubits IBM-Q quantum devices. This quantum computer has nonperfect gates based on superconducting qubits, and, therefore, we analyzed the impact of the CNOT errors and CNOT-depth on the fidelity of the circuit.