Stacked Chip Scale Package Research Articles

Effects of outlet vent arrangement on air traps in stacked-chip scale package encapsulation

The current paper analyzes the effect of outlet vent arrangements on the air traps and pressure distribution of a stacked-chip scale package (S-CSP) during encapsulation. A three-dimensional model of S-CSP is created using GAMBIT and analyzed using FLUENT code. In the molding process, the epoxy molding compound flow behavior calculated using the Castro–Macosko viscosity model by considering the curing effect, and the volume of fluid technique are applied for flow front tracking. The viscosity model is written in C language and compiled using User-Defined Function in FLUENT code. Three different types of outlet vent arrangement are considered in the analysis, namely, Type A, Type B, and Type C. Type A, which has the minimum outlet vent area, shows the minimum air trap and the highest average pressure distribution. The simulation results of the flow front profiles agree well with previous experimental results.

Over Molding Process Development for a Stacked Wafer-level Chip Scale Package with Through Silicon Vias (TSVs)

Over Molding Process Development for a Stacked Wafer-level Chip Scale Package with Through Silicon Vias (TSVs)

Stress Buildup of Sn3.5Ag Soldered Stacked CSPs to Board-Level Drop Impact

Solder balls, albeit mechanically soft, are the only structural support to the stacking of chip-scale packages (CSPs). This paper investigates the structural response of a Sn3.5Ag soldered bi-level stacked CSP module to board-level drop impact per the JEDEC criteria, and quantifies the stress buildup in the critical solder balls. The structural response is understood by tracking the force transmission through this 3-D packaging assembly by an elastic structural analysis, in which the solder plasticity is deliberately excluded. The elastic analysis shows that the solder balls at the ball-out level, which is the bottom level of the stacked package interconnecting to the mounting board, suffer the severest stress buildup. The results suggest that understanding of relative vibration amplitude among each level of the stacked package and the mounting board enables a good estimation of the location of critical solders without detailed modeling. For this stacked CSP module, the critical solders locate at the corners of the center package at the ball-out level. Solder balls are more severely loaded in the 0° orientation drop, about one order of magnitude larger than in the 90° orientation drop. The critical solder balls will be promptly loaded to a state in the highly plastic regime after the impact is initiated, as suggested by detailed finite element analysis which accounts for the strain-hardening of Sn3.5Ag. Larger plastic strain accumulation is observed near the interfaces to the solder pad. The solder balls at the higher level of the stacked packages are likely always free of plastic deformation in the drop testing.

Effect of vertical stacking dies on flow behavior of epoxy molding compound during encapsulation of stacked-chip scale packages

This paper presents three dimensional (3D) simulation of flow visualization in the encapsulation of stacked-chip scales packages (S-CSP), using finite volume method. The S-CSP model is constructed using GAMBIT and simulated using FLUENT CFD software. The epoxy molding compound is Hitachi CEL-9200 XU (LF) and its flow is assumed laminar and incompressible. Cross viscosity model and volume of fluid technique are applied for flow front tracking of the encapsulant. The meshing is performed using tetrahedral elements and the discretization is done by first order upwind scheme. SIMPLE algorithm is selected for solving the governing equations. The top view and 3D view of simulation flow front profiles in the encapsulation process are presented. The percentage of filled volume versus filling time, viscosity versus shear rate and number of voids versus rows of stacked die are plotted. The temperature and pressure distributions within the mold cavity during the encapsulation process are also observed. Further, the possibility and cause of void formation during the encapsulation process are analyzed and discussed in detail. The number of vertical stacking dies and horizontal rows of packages are found to be crucial in the void formation. The numerical results are compared with previous experimental results and found in good conformity.

Assembly reliability assessment and life estimation for a stacked area array device

Memory module manufacturers face an ongoing challenge to incorporate more functionality and superior performance with each new generation of product offering. The growth in demand for memory capacity is surpassing the pace at which memory component manufacturers are able to cost-effectively produce the next-generation of monolithic memory devices. Stacking components helps in the transition to higher-density memory while the design and production capability for the next-generation of memory devices is being developed. However, on the other hand, the complex nature of stacked Chip Scale Package (CSP) components mandates a thorough review of the assembly processes and a detailed reliability assessment for these packages. The research objective was to study the assembly reliability of stacked CSP components assembled on a densely populated lead-free memory module utilizing mirror imaged component placements. The assessment was carried out using thermal cycling and mechanical shock tests. The data collected from thermal cycling was also used for failure modeling and life estimation. The methodology for estimating field life was established and the field life was estimated for a server application. The results proved that stacked CSP components can be reliably assembled. The module using stacked CSP components surpassed the life expectancy for server applications, which is 10 years.

Reliable Lead-Free Rework Process for Stacked CSP Components

Memory module manufacturers face an ongoing challenge to incorporate more functionality and superior performance with each new generation of product offering. The growth in demand for memory capacity is surpassing the pace at which memory component manufacturers are able to cost-effectively produce the next generation of monolithic memory devices. This drives the need for utilizing stacked components for memory module assemblies. The complex nature of stacked chip-scale package (CSP) components coupled with a lead-free process presents unique rework challenges that needed to be studied and addressed. Reworking a CSP is complicated as the solder joints are hidden underneath the component. The process window available for the lead-free rework process is very narrow. There are number of other critical factors, which complicate and affect the repeatability of the rework process. The complications only increase with the use of stacked CSP devices. The rework of package stacked CSP components, which are complex in nature, is a daunting task. The key issues and observations with regard to the issues and challenges associated with the lead-free rework of mirror-imaged package stacked CSP components has been presented in this paper. In addition, the paper also provides a recipe for reliably reworking these packages.

A Study on the Effect of Epoxy Molding Compound (EMC) Rheology During Encapsulation of Stacked-CHIP Scale Packages (S-CSP)

The numerical and experimental investigations of three-dimensional (3-D) mold filling during encapsulation process in stacked-chip scale package (S-CSP) are presented. The finite difference method (FDM) based on Navier—Stokes equations has been employed for the flow analysis in the mold cavity. The mold flow is assumed to be non-Newtonian and non-isothermal. The proposed models can take care of polymer rheology with cure effect (Castro—Macosko model) and without cure effect (Cross model). A package with five, six, and seven overhang stacking dies without wire bonds is considered for simulation. The epoxy molding compound (EMC) used is HITACHI CEL-9200. The effects of gap between die top and mold cap surface, and between adjacent dies on flow rheology are analyzed and presented. The flow retardation in the limitation region (gap region) and smooth flow in the free region of the package is being predicted. Higher initial conversion of EMC demonstrated higher viscosity and slower melt front advancement especially under the overhang area of same die stacking region and critical gap between the die and mold cap. The void mechanism occurred due to unbalanced mold flow and critical gap clearance. The simulation results are verified with those obtained from a typical electronic industry and found in good agreement. From the results; the Castro—Macosko model is found to be more stable and reliable on the flow rheology.

Study on the Effect of Stack Thickness During Encapsulation of Stacked-Chip Scale Packages (S-CSP)

Development of microelectronics continues toward further miniaturization. Stacked-chip scale packages (S-CSPs) can address the issues associated with high-density packaging with reduction in cost and greater improvements in functional performance. However, the problems involved in the encapsulation of S-CSPs are complex because of the crucial gap thickness between the die top and mold surface. Air traps, void formation, and flow retardation are major problems. In this paper, three-dimensional (3-D) mold filling with different arrangements of stacked dice in S-CSPs is investigated with the objective of determining the optimum number of stacked dice. A 2-D view on the top surface is chosen because it is easier to visualize the melt front compared with the 3-D view. It is found that the time needed to fill the package and the chance of void formation increase with increasing number of stacked dice.

Study of flow visualization in stacked-Chip Scale Packages (S-CSP)

The stacked-Chip Scale Package (S-CSP) is a new technology that provides high density of the package. It enables to stack the die in a single package. The S-CSP is widely adopted in portable multi-media products. However, the resin flow through a thin surface and wide filling area is of concern. Therefore, this paper presents a study of flow visualization during encapsulation process in S-CSP. The Navier–Stokes equation has been solved by the finite different method. For non-linear terms, the Kawamura and Kuwahara technique has been adopted in the flow analysis. Pseudo-concentration based on the volume of fluid (VOF) technique was used to track a melt fronts for each time step. The numerical model has been verified by comparing the prediction with the experimental results. The numerical results show good agreement with the experimental results. The prediction also shows that the short shot problem that occurred for the die top clearance is lower than 0.25 mm.

Thermal characterization of overmolded underfill materials for stacked chip scale packages

Stacked chip scale package (SCSP) is a new electronic packaging technology for non-CPU products, such as hand-held computing and communication devices. In this technology, one or more wire-bonded silicon chips are stacked on top of another flipped silicon chip, and an overmolded underfill encapsulant is used to both encapsulate and underfill the wire-bonded chip and the flip chip in a single process. In this paper, the cure behavior, thermal stability, filler content, and thermomechanical properties of five overmolded underfill materials have been studied using DSC, TGA, TMA, and DMA. Results showed that there is a strong correlation between thermomechanical properties and the filler content of the material. Based on measured thermomechanical properties, a “figure-of-merit” approach was used to estimate the thermal stress induced in the package upon cooling. Results showed that an OMUF material with a low T g, low coefficient of thermal expansion (CTE), and low modulus can effectively reduce the package thermal stress. The reliability results are in good agreement with the predictions based on thermal stress estimation.

Characteristics of Si Integrated Antenna for Inter-Chip Wireless Interconnection

The characteristics of a small-size integrated dipole antenna on Si have been evaluated for use in inter-chip wireless interconnections and the measured characteristics are compared with the results obtained by 3D finite element simulation. The measured inter-chip transmission coefficients for a 0.02 mm2 dipole antenna pair manually separated by 10.5 mm each other in the horizontal plane and in a omit plane where the receiver chip is 2.6 mm higher than the transmitter chip were -42.7 dB and -57.5 dB at 20 GHz when the antennas were fabricated on a high-resistivity Si substrate and on standard Si substrate, respectively. This shows the feasibility of using integrated dipole antennas for wireless clock distribution and data transmission in future 3D ICs or in stacked chip scale packaging.

Improving the deflection of wire bonds in stacked chip scale package (CSP)

The deformation of gold wire bonds during transfer molding of stacked chip scale package (CSP) can seriously cause wire crossover and shorting. The major challenges of the stacked CSP development are to reduce the wire sweep (deflection), and make the sufficient space clearance between the wires of first to second die. In this paper, M shape wire looping program is developed to increase the wire sweep resistance in the stacked CSP. Both linear elastic finite element analysis and experiments based on wire bonding and molding process evaluation are conducted. It is found that M shape looping program is much better than conventional normal wire shape in terms of wire sweep resistance after molding. X-ray and scanning electronic microscopy (SEM) can verify the improvement of wire deflection after chemical de-capsulation. It is believed that using M shape looping program can efficiently overcome the risk of wire shorting and improve the yield of wire bonds in high volume production of stacked CSP.

Board level reliability of a stacked CSP subjected to cyclic bending

Second (board) level reliability of a stacked chip scale package (SCSP) under cyclic bending is conducted to evaluate the structural integrity of solder interconnects. The test vehicle (on-board SCSP) is simply supported at both ends and subjected to repetitive deflection in the middle (three-point bend). Cyclic deformation histories such as sinusoidal, triangular, and square waveforms are examined. Tremendous joint damage is observed as square-wave loading history was applied. Approximately 80% fatigue life degradation is found by bending several thermally aged samples having Ni/Au surface finish on Cu pads of package substrates and printed circuit boards. The observed failure mode is a brittle type fracture of intermetallic compound system, which is also known as effects of solder embrittlement. Measured fatigue life is characterized by two-parameter Weibull model with cumulative damage plot for each test condition. In addition to the comparisons of characteristic fatigue life for various package configuration and cyclic bending conditions, failure analysis is also employed to identify failure sites and mechanisms such as crack initiation and continuous growth to the complete fracture of solder joints.

AMKOR expands stacked chip-scale package capacity and 3D packaging family

AMKOR expands stacked chip-scale package capacity and 3D packaging family