Reliable Lead-Free Rework Process for Stacked CSP Components

Abstract

Memory module manufacturers face an ongoing challenge to incorporate more functionality and superior performance with each new generation of product offering. The growth in demand for memory capacity is surpassing the pace at which memory component manufacturers are able to cost-effectively produce the next generation of monolithic memory devices. This drives the need for utilizing stacked components for memory module assemblies. The complex nature of stacked chip-scale package (CSP) components coupled with a lead-free process presents unique rework challenges that needed to be studied and addressed. Reworking a CSP is complicated as the solder joints are hidden underneath the component. The process window available for the lead-free rework process is very narrow. There are number of other critical factors, which complicate and affect the repeatability of the rework process. The complications only increase with the use of stacked CSP devices. The rework of package stacked CSP components, which are complex in nature, is a daunting task. The key issues and observations with regard to the issues and challenges associated with the lead-free rework of mirror-imaged package stacked CSP components has been presented in this paper. In addition, the paper also provides a recipe for reliably reworking these packages.