Study on the Effect of Stack Thickness During Encapsulation of Stacked-Chip Scale Packages (S-CSP)

Abstract

Development of microelectronics continues toward further miniaturization. Stacked-chip scale packages (S-CSPs) can address the issues associated with high-density packaging with reduction in cost and greater improvements in functional performance. However, the problems involved in the encapsulation of S-CSPs are complex because of the crucial gap thickness between the die top and mold surface. Air traps, void formation, and flow retardation are major problems. In this paper, three-dimensional (3-D) mold filling with different arrangements of stacked dice in S-CSPs is investigated with the objective of determining the optimum number of stacked dice. A 2-D view on the top surface is chosen because it is easier to visualize the melt front compared with the 3-D view. It is found that the time needed to fill the package and the chance of void formation increase with increasing number of stacked dice.