Stacked Chip Package Research Articles

Nondestructive monitoring of annealing and chemical–mechanical planarization behavior using ellipsometry and deep learning

The Cu-filling process in through-silicon via (TSV-Cu) is a key technology for chip stacking and three-dimensional vertical packaging. During this process, defects resulting from chemical–mechanical planarization (CMP) and annealing severely affect the reliability of the chips. Traditional methods of defect characterization are destructive and cumbersome. In this study, a new defect inspection method was developed using Mueller matrix spectroscopic ellipsometry. TSV-Cu with a 3-μm-diameter and 8-μm-deep Cu filling showed three typical types of characteristics: overdishing (defect-OD), protrusion (defect-P), and defect-free. The process dimension for each defect was 13 nm. First, the three typical defects caused by CMP and annealing were investigated. With single-channel deep learning and a Mueller matrix element (MME), the TSV-Cu defect types could be distinguished with an accuracy rate of 99.94%. Next, seven effective MMEs were used as independent channels in the artificial neural network to quantify the height variation in the Cu filling in the z-direction. The accuracy rate was 98.92% after training, and the recognition accuracy reached 1 nm. The proposed approach rapidly and nondestructively evaluates the annealing bonding performance of CMP processes, which can improve the reliability of high-density integration.

Micro Solder Joint Reliability and Warpage Investigations of Extremely Thin Double-Layered Stacked-Chip Packaging

Abstract To overcome the limited operational speed for nanoscaled transistors, scaling electronic devices to small and thin packaging and high-density arrangements have become the technological mainstream in designing versatile packaging architectures. Among these, a promising candidate is a three-dimensional integrated circuit (3D-IC) package due to its excellent capability of heterogeneous integration. However, sequential reliability is a troublesome concern given the complex packaging structure, especially for the assembly of microsolder joints. To address this issue, we propose a double-layered, thin stacked chip package under the application of temperature cycling load. The packaging warpage and creep impact of SnAg microsolder joints on their fatigue lifespan are examined separately. Nonlinear material/geometry finite element analysis (FEA) is used on important designed factors, including the elastic modulus of underfill, chip thickness, and the radius and pitch of through silicon via (TSV). The simulated results indicate that the best fatigue lifetime of SnAg microsolder joint can be achieved at 10 μm of each chip thickness, 230 μm and 5 μm for TSV pitch and radius within the examined designed extent. Moreover, a hard underfill material requires consideration when the mounted chips thicken. Consequently, reliability significantly improves by dispersing thermomechanical stress/strain of the SnAg microjoints to neighboring underfill and related packaging components, especially for large TSV array spacing.

Demonstration of an Equivalent Material Approach for the Strain-Induced Reliability Estimation of Stacked-Chip Packaging

A huge shift in classical system integration composed of heterogeneous and homogeneous substances from 2D to 2.5D or even 3D assembly is a promising solution to satisfying the requirements of electronic packages, such as high operating speed, multifunctionality, and low form factor, under the physical limits of nanoscaled transistors and bottlenecks in related fabrication technologies. However, considerable dimension mismatch is introduced into the entire packaging by numerous microbumps ( ${\mu }$ -bumps) with complicated compositions in existing frameworks. In addition, failure location and precise reliability estimation are difficult to achieve when the layout of high-density ${\mu }$ -bump arrays is considered. To solve this urgent issue, an equivalent material characteristic methodology for ${\mu }$ -bump arrays based on finite element analysis (FEA) is developed in this study. A test vehicle for chip-on-chip packaging with wafer-level underfill is set up to obtain the mechanical characteristics of equivalent materials for the portion with internal ${\mu }$ -bump arrays. The equivalent plastic strain generation of the tin layer is simulated by systematically comparing the numerical convergence of FEA under the assumption that the lead-free solder forms ${\mu }$ -bumps within after the assembly process. Analytic results indicate that at least four rows of actual ${\mu }$ -bumps from the outermost edge of the ${\mu }$ -bump array are required to ensure numerical accuracy in contrast with the result obtained from the actual model of the present packaging structure.

Inductance Modeling of Interconnections in 3-D Stacked-Chip Packaging

This letter explores the inductance of interconnections including through-silicon vias (TSVs) and redistribution layers (RDLs) in 3-D stacked-chip packaging. It is described that the common summing method of partial inductances will result in some deviations from the full inductance. Then, the inductances of TSVs and RDLs are, respectively, calculated and are verified by a commercial electromagnetic simulator. The modified formulas are proposed for the more accurate full inductance model, which is derived from different design physical parameters of the interconnections. The side effect of a general summing method can be reduced a lot by our proposed analytical model.

Role of Plastic Behaviors of Ni3Sn4 Intermetallic Compound on Solder Joint Reliability

The study aims at investigating the influences of the elastoplastic behaviors of the micrometer-thick Ni3Sn4 intermetallic compound (IMC) observed in the Cu/Ni/Sn3.5Ag solder joints of 3-D chip stacking package on the solder joint reliability under accelerated thermal cycling (ATC). The IMC’s elastoplastic properties are characterized through the developed forward-reverse analysis algorithm, which integrates parametric finite element analysis (FEA) of instrumented indentation, dimensional analysis, and an experimental instrumented indentation test. The algorithm is first applied to characterize the elastoplastic behaviors of an electrodeposited Cu thin film, the results of which are compared with the known data, followed by a test on the thin Ni3Sn4IMC. The predicted elastoplastic properties are input to the ATC FEA model of the package to simulate the solder joint mechanical response, by which the corresponding fatigue life is assessed using a Coffin–Manson model. The simulation is validated against the experimental data. Besides, the prediction is compared with that without the plastic effect. Results show that despite bulk IMCs being normally elastic, brittle, and hard, the thin Ni3Sn4 IMC possesses a highly ductile (plastic) and strain-hardening behavior. Moreover, taking the plastic behavior of the thin Ni3Sn4 IMC into account helps improve the prediction of the solder joint fatigue life of the package.

3-D TSV Six-Die Stacking and Reliability Assessment of 20- $\mu$ m-Pitch Bumps on Large-Scale Dies

3-D integration typically involves multiple chips stacking with large numbers of interconnections within each chip. There are several fundamental technology challenges that need to be addressed in order to realize 3-D integration, such as Cu through-silicon via (TSV) expansion, transistor degradation or open failures on Cu contamination, microbump stress, and so on. The reliability issues on TSV and microbumps are very critical not only for a stacked chip package, but also during wafer-level processes. In this paper, the authors successfully stacked six chips with a thickness of 50 $\mu \text{m}$ and assessed their reliability. Each chip consists of 122054 bumps with a bump diameter of $10~\mu \text{m}$ and a pitch of 20 $\mu \text{m}$ . These bumps were built directly on TSVs, which have a diameter of $5~\mu \text{m}$ . Measured electrical resistance is well matched with calculated electrical resistance. Finally, this paper presents the reliability results of the 3-D IC packages that are embedded in molding compound.

First-principles Calculation of Interfacial AdhesionStrength and Electromigration for the Micro-bumpInterconnect of 3D Chip Stacking Packaging

First-principles Calculation of Interfacial AdhesionStrength and Electromigration for the Micro-bumpInterconnect of 3D Chip Stacking Packaging

FSI Analysis of the Effect of Aspect Ratio of Stacked Chip in Encapsulation Process of Moulded Underfill Packaging

Finite volume method (FVM) based simulation of 3D fluid-structure interaction (FSI) of stacked chip package during the encapsulation process of moulded underfill (MUF) in different aspect ratio is presented in this paper. The 3D model of flip chip package is built and meshed using ANSYS ICEM, and simulated by FLUENT software. Castro–Macosko viscosity model and volume of fluid (VOF) technique are applied for flow front tracking of the encapsulant. Curing kinetics is taken into consideration in the simulation using Kamal’s equation. To solve the Castro–Macosko and Kamal models, suitable user defined functions (UDFs) are developed using MS VISUAL STUDIO.NET software and incorporated into the FLUENT. The parameter such as different aspect ratio of stacked die of mold cavity on the flow front behaviour is mainly studied. Mechanical stresses experienced by the silicon die will also be monitored for risk of die cracking. The visualisation of the 3D stacking-chip package encapsulation process was presented at different filling times. The encapsulation model aided a clear visualisation and improved fundamental understanding of the design of a 3D integrated circuit encapsulation. The proposed analysis is expected to be a reference and guide in the design and improvement of 3D integration packages.

Development of Equivalent Material Properties of Microbump for Simulating Chip Stacking Packaging.

A three-dimensional integrated circuit (3D-IC) structure with a significant scale mismatch causes difficulty in analytic model construction. This paper proposes a simulation technique to introduce an equivalent material composed of microbumps and their surrounding wafer level underfill (WLUF). The mechanical properties of this equivalent material, including Young’s modulus (E), Poisson’s ratio, shear modulus, and coefficient of thermal expansion (CTE), are directly obtained by applying either a tensile load or a constant displacement, and by increasing the temperature during simulations, respectively. Analytic results indicate that at least eight microbumps at the outermost region of the chip stacking structure need to be considered as an accurate stress/strain contour in the concerned region. In addition, a factorial experimental design with analysis of variance is proposed to optimize chip stacking structure reliability with four factors: chip thickness, substrate thickness, CTE, and E-value. Analytic results show that the most significant factor is CTE of WLUF. This factor affects microbump reliability and structural warpage under a temperature cycling load and high-temperature bonding process. WLUF with low CTE and high E-value are recommended to enhance the assembly reliability of the 3D-IC architecture.

Microvia and through-Hole Filling By Electroplating for Electronic Circuit Fabrication

Electronic products, such as computers, smart phones, laptops and so on, need chips to perform their functions. These chips have many devices, which need to be integrated and connected with each other. To expand the functions of electronic products, more MOS have not met the requirement yet compared with more chips. Therefore, the concept of three-dimensional (3D) chip stacking packaging is proposed. To meet high density interconnection (HDI), through silicon vias (TSVs), through glass vias (TGVs) used as conducting channels of chip stacking need to be fully filled with metal (e.g., copper or nickel-tungsten alloy), and microvia and through hole designed in IC packaging substrates and printed circuit boards (PCBs) need to be fully filled with copper as well. These filling plating technologies have similar process steps but their feature size is totally different.1-11 Herein, we will review these process steps and propose novel filling plating process steps and technologies, including highly selective microvia filling without copper deposition on the outside plane surface, direct through hole filling without usage of a conducting template, TSV filling using CoWP as a barrier layer and electroless copper as a seed layer, TSV filling using reduced graphene oxide (rGO) as barrier and seed layers, TSV filling without copper but rGO combining with NiW alloy, TGV filling using electroless copper as a seed layer and direct pattern copper electroplating onto a glass wafer by using Al-doped ZnO (AZO) as an adhesive and conducting layer.

Synchrotron Radiation Microtomography for Large Area 3D Imaging of Multilevel Microelectronic Packages

3D x-ray computed tomography (CT), using conventional laboratory-based x-ray sources, has been used in the past to image multiple levels of interconnects in 3D microelectronic packages. These conventional x-ray sources can provide high resolution images with throughput times (TPT) of several hours. However, this can only be performed on localized areas of about 1–2 mm2, which gravely limits the application of 3D x-ray CT in the field of microelectronic packages with sizes usually in the range of 100–3600 mm2. An alternative to laboratory-based x-ray sources is synchrotron radiation, which can produce large area collimated beams for high flux x-ray imaging over a much larger field of view (FOV) than conventional sources. Synchrotrons can potentially image an entire 3D stacked chip package at high resolutions in less than an hour. Here, we present results using the micro-CT line at the advanced light source synchrotron to image an entire 16 × 16 mm system in a package in times as low as 3 min, demonstrating several orders of magnitude increase in the ratio of FOV to TPT as compared to laboratory-based x-ray methods.

Analysis of 3D TSV Vertical Interconnection Using Pre-applied Nonconductive Films

Much research has been carried out to realize through-silicon via (TSV) technology for three-dimensional (3D) chip stacking packaging. A vertical chip interconnection method using Cu/Sn-Ag bumps and nonconductive films (NCFs) is one of the most promising approaches for 3D TSV vertical interconnection. In this work, the relationship between the viscosity of pre-applied NCFs and loading forces was investigated to predict the gap change between a TSV chip and a substrate chip. Existing theories of squeeze flow are adapted to predict the gap change of a real TSV chip and a substrate chip during TSV bonding using a simplified model. The real gaps measured during bonding of test dies were matched to check the validity of the prediction model. Considering the thixotropy of NCFs, the prediction well matched the real gap changes between bumped TSV chips and substrate chips during bonding.

Evaluation of Die Strength by Using Finite Element Method With Experiment Validation

3-D chip stacking packaging is becoming increasingly popular in the electronics packaging industry because the demand of current market has focused on cheaper products with higher performance characteristics and smaller form factors. Silicon wafers must be ground using wafer-thinning processes to achieve smaller packaging sizes. However, cracks may form in the silicon chips during stacking or while the device is in use. In this paper, the ball-breaker test is used to determine the maximum allowable force on a (1 0 0) silicon die. Finite element (FE) analysis using the commercial software ANSYS/LS-DYNA3-D is introduced to calculate the strength of the silicon die and compared with the experimental findings shows that the results are consistent with Hertzian contact theory. The effects of silicon die thickness and foundation material on the silicon die strength are also discussed in this paper. As the applied force increases, a crack appears on the edge of the contact area and propagates within the die. A decrease in die thickness results in the formation of radial cracks on the bottom surface as well as significant bending effects on the test die. The initial failure may originate from the radial crack and propagate toward the top surface of the die leading to die breakage. The strengths determined in this experiment decrease as the test die becomes thinner. Furthermore, if the insignificant bending behavior is observed, simulation results show that the maximum allowable force on a silicon die increases when a softer foundation material is used. However, a thin test die placed on a soft material is considerably easy to break because the tensile stress on the bottom surface of the die caused by the rapid increase in bending behavior significantly affects die breakage.

Drop Impact Reliability Analysis of 3-D Chip-on-Chip Packaging: Numerical Modeling and Experimental Validation

This paper aims at investigating the drop impact solder interconnect reliability of an advanced ultra-fine-pitch 3-D integrated circuit chip stacking packaging in accordance with JEDEC board-level test specification through finite-element (FE) simulation and experimental testing. To characterize the transient dynamic responses of the package, ANSYS/LS-DYNA incorporated with the Input-G method is applied. To well simulate the mechanical behaviors of the solder interconnects, a strain-rate-dependent elastoplastic Johnson-Cook constitutive model for the Sn3.5Ag solder is applied. In addition, an inverse calculation is carried out to identify the overall structural damping of the dynamic system. Furthermore, a JEDEC-compliant drop tester is used to conduct the drop test, where failure analysis is performed using an optical microscope. Moreover, a simplified Darveaux fatigue life prediction model is constructed based on the calculated strain energy densities at different JEDEC test conditions together with the corresponding drop test data. To demonstrate the validity of the developed fatigue life prediction model, a confirmatory experiment is performed. Finally, parametric FE study incorporated with experimental design is performed to seek a design guideline for enhanced solder interconnect reliability under drop impact. Both the experimental and simulation data reveal that underfill can greatly enhance the drop impact reliability of the solder interconnects. In addition, the cornered interconnects and even package in a one-component configuration would fail earlier than the central ones, with a cohesive fracture in the Sn3.5Ag solder rather than the intermetallic compound (IMC) and its interface. Besides, an increasing IMC thickness reduces the drop impact solder interconnect reliability while enhancing the thermal cycling one.

Reliability Challenges of 3-D Stacked Chip Package With Through-Silicon-Via (Invited talk)

not Available.

Reliability estimation and failure mode prediction for 3D chip stacking package with the application of wafer-level underfill

With the impressive size shrinkage of advanced transistors and Cu/low-k interconnect systems, the introduction of through-silicon via integrated with three-dimensional (3D) chip-stacking approaches has become one of the major packaging technologies to meet the desired requirements of multifunctionality. The use of microbump (@m-bump) interconnected silicon chips to ensure the reliability of the interconnections is regarded as a critical issue that must be resolved. In this research, wafer-level underfill (WLUF) joined with flip-chip technology are proposed, and a nonlinear finite element analysis, combined with a process-oriented simulation technique, is used to investigate the packaging assembly effect of the WLUF thermal-compressive process. The stress predictions during the temperature cycling test is also systematically explored. The proposed simulation methodology is successfully validated through comparison with experimental data. The analytical results indicate that both the assembly and thermomechanical reliabilities of @m-bumps are determined by the arrangement of the @m-bump arrays. Consequently, the optimal designs of @m-bump layouts within the chips must be seriously considered, given that silicon chips thinner than 100@mm are assembled in 3D advanced packages.

IMC growth reaction and its effects on solder joint thermal cycling reliability of 3D chip stacking packaging

The study aims at assessing the growth reaction of the Ni3Sn4 intermetallic compound (IMC) during bonding process and its dependences on the thermal-cycling reliability of the Cu/Ni/SnAg micro-joints of an advanced 3D chip stacking package under accelerated thermal cycling (ATC) loading. The growth reaction of the IMC during bonding process is also predicted through experiment and classical diffusion theory, and the relation between the IMC thickness and bonding process temperature and time is derived according to the predicted activation energy of the chemical reaction between Sn and Ni by experiment. Moreover, the micro-joint reliability prediction is made using finite element (FE) analysis incorporated with an empirical Coffin–Manson fatigue life prediction model and also ATC experimental test. To facilitate the FE modeling, the temperature-dependent thermoelastic properties of both single crystal and polycrystalline Ni3Sn4 IMC are characterized through molecular dynamics simulation and the Voigt–Reuss bound and Voigt–Reuss–Hill approximation.Results show that monoclinic single crystal Ni3Sn4 reveals a high elastic anisotropy or direction dependence of elasticity. The diffusion reaction of Sn and Ni exhibits that a longer bonding process time and a higher bonding temperature could not only increase the IMC thickness but also vary its surface morphology. In addition, the thermal–mechanical performance of the micro-joints is strongly affected by the geometry and material of IMC layer, where IMC with a thicker thickness, a less Young’s modulus, a smaller CTE and even a more rounded surface morphology can better the reliability.

Low Temperature Curing - Aqueous Base Developable Photoimageable Dielectric for WLP (Wafer Level Packaging)

As advanced packaging application space evolves and continues to deviate from the conventional shrinkage pathway predicted by Moore's law, material suppliers need to continue to work with OEMs, OSATs and Foundries to identify specific opportunities. One such opportunity continues to present itself in developing new materials to support new platforms for next generation products to support 3D chip stacking and TSV applications. The newer material sets can be established to meet more challenging design requirements associated with the demands, presented by the application from both a physical/lithographical processing and design perspective. Next generation packages requires the development of new dielectric materials that can support both the physical demands of 3D chip stacking and TSV package design aspects while maintaining strengths of the existing material platform. While vertical integration necessitates the use of thinned substrates and its associated integration challenges, there is a continuing need to support horizontal shrinkage typical of the Moore's Law, which pushes the lithography envelope requiring finer pitch and smaller feature resolution capability. This presentation identifies the strategy we have taken and highlights approach taking in the development of low temperature curable photoimageable dielectric materials with enhanced lithographic performance. We will discuss the methodology used to create benzocyclobutene based dielectric material curable at 180 °C and show how lithographic performance can be tuned to allow sub 5 micron via using broad band illumination. Finally we will review the impact of low temperature processing on the mechanical, thermal and electrical properties of this novel photoimageable dielectric material.

Stacked Chip Thermal Model Validation using Thermal Test Chips

INTRODUCTION Increasing demands on density, functionality and performance in small package footprints has lead to a higher market share for stacked-chip packaging. This trend has brought with it the need for better understanding of thermal issues associated with removing heat from the various chips in the stack. Typically, thermal simulation models are used to gain an insight to heat flow issues in complex multi-chip packages. The validity of the models and the assumptions drawn from the model results are questionable unless measurements are used to validate the model results.

Chip warpage model for reliability prediction of delamination failures

A new experimental method to predict reliability for ACA type packages under temperature cycling is developed and proposed. The method introduces a new damage parameter that can be easily measured by experiment. It is proved that the linear elastic parameter, dw/dT which represents the rate of change of chip warpage with respect to temperature, efficiently reflects the common failure mechanism of ACA type packages, the interfacial delamination between the chip and the adhesive. It is demonstrated, both experimentally and numerically, that the size of delamination affects the warpage behavior of the chip. The dw/dT of the chip is monitored in real time using laser interferometers under thermal fatigue cycles up to 3000. The gradual decrease in warpage due to progressive increase in delamination is clearly emerged. As a result, a reliability curve that can predict the size of delamination and remained life is obtained. The new long-term reliability prediction method developed in this study can be applied to various advanced packages, e.g. underfilled flip–chip or TSV stacked chip packages, that embrace interfacial delamination as primary failure mode.